Table 206. Fsmc_Bcrx Bit Fields; Table 207. Fsmc_Btrx Bit Fields - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)
The differences with mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.

Table 206. FSMC_BCRx bit fields

Bit No.
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0

Table 207. FSMC_BTRx bit fields

Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
1339/1422
Bit name
Reserved 0x000
CBURSTRW 0x0 (no effect on asynchronous mode)
Reserved 0x0
Set to 1 if the memory supports this feature. Otherwise keep
ASYNCWAIT
at 0.
EXTMOD 0x1
WAITEN 0x0 (no effect on asynchronous mode)
WREN 0x1
WAITCFG As needed
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Set according to memory support
MWID As needed
MTYP As needed
MUXEN 0x0
MBKEN 0x1
Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) in
DATAST
read.
Duration of the middle phase of the read access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) in read.
ADDSET
Minimum value for ADDSET is 0.
Doc ID 018909 Rev 4
Value to set
Value to set
RM0090