Nor/Psram Control Registers - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)
32.5.6

NOR/PSRAM control registers

The NOR/PSRAM control registers have to be accessed by words (32 bits).
SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4)
Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4
Reset value: 0x0000 30DX
This register contains the control information of each memory bank, used for SRAMs, ROMs
and asynchronous or burst NOR Flash memories.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Bits 31: 20
Bit 19 CBURSTRW: Write burst enable.
Bits 18: 16
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
Bit 14 EXTMOD: Extended mode enable.
Bit 13 WAITEN: Wait enable bit.
Bit 12 WREN: Write enable bit.
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Reserved
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Reserved, must be kept at reset value.
For Cellular RAM (PSRAM), the bit enables the synchronous burst protocol during
write operations. The enable bit for the synchronous burst protocol during read access
is the BURSTEN bit in the FSMC_BCRx register.
0: Write operations are always performed in asynchronous mode
1: Write operations are performed in synchronous mode.
Reserved, must be kept at reset value.
This bit enables/disables the FSMC to use the wait signal even during an asynchronous
protocol.
0: NWAIT signal is not taken in to account when running an asynchronous protocol
(default after reset)
1: NWAIT signal is taken in to account when running an asynchronous protocol
This bit enables the FSMC to program the write timings inside the FSMC_BWTR
register, thus resulting in different timings for read and write operations.
0: values inside FSMC_BWTR register are not taken into account (default after reset)
1: values inside FSMC_BWTR register are taken into account
This bit enables/disables wait-state insertion via the NWAIT signal when accessing the
Flash memory in synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after
the programmed Flash latency period)
1: NWAIT signal is enabled (its level is taken into account after the programmed Flash
latency period to insert wait states if asserted) (default after reset)
This bit indicates whether write operations are enabled/disabled in the bank by the
FSMC:
0: Write operations are disabled in the bank by the FSMC, an AHB error is reported,
1: Write operations are enabled for the bank by the FSMC (default after reset).
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