Otg_Hs Programming Model; Core Initialization - ST STM32F40 Series Reference Manual

RM0090
Table 184. OTG_HS register map and reset values (continued)
Offset Register
OTG_HS_DOE
PTSIZ0
0xB10
Reset value
OTG_HS_DOE
PTSIZ1
0xB30
Reset value
OTG_HS_DOE
PDMA1
0xB34
Reset value 0
OTG_HS_DOE
PDMAB1
0xB3C
Reset value 0
OTG_HS_DOE
PTSIZ2
0xB50
Reset value
OTG_HS_DOE
PDMA2
0xB54
Reset value 0
OTG_HS_DOE
PDMAB2
0xB5C
Reset value 0
OTG_HS_DOE
PTSIZ3
0xB70
Reset value
OTG_HS_DOE
PDMA3
0xB74
Reset value 0
OTG_HS_DOE
PDMAB3
0xB7C
Reset value 0
OTG_HS_PCG
CCTL
0xE00
Reset value
Refer to
31.13

OTG_HS programming model

31.13.1

Core initialization

The application must perform the core initialization sequence. If the cable is connected
during power-up, the current mode of operation bit in the Core interrupt register (CMOD bit
in OTG_HS_GINTSTS) reflects the mode. The OTG_HS controller enters host mode when
an "A" plug is connected or peripheral mode when a "B" plug is connected.
This section explains the initialization of the OTG_HS controller after power-on. The
application must follow the initialization sequence irrespective of host or peripheral mode
operation. All core global registers are initialized according to the core's configuration:
STUP
CNT
Reserved
0 0
PKTCNT
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PKTCNT
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PKTCNT
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Table 2 on page 52 for the register boundary addresses.
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
0
0 0 0 0 0 0 0 0 0
DMAADDR
0 0 0 0 0 0 0 0 0
DMABADDR
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
DMAADDR
0 0 0 0 0 0 0 0 0
DMABADDR
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
DMAADDR
0 0 0 0 0 0 0 0 0
DMABADDR
0 0 0 0 0 0 0 0 0
Reserved
Reserved
0
XFRSIZ
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
XFRSIZ
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
XFRSIZ
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
XFRSIZ
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
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