Figure 418. Asynchronous Wait During A Read Access - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)
1. Memory asserts the WAIT signal aligned to NOE/NWE which toggles:
2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then
DATAST
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 418
memory access after WAIT is released by the asynchronous memory (independently of the
above cases).

Figure 418. Asynchronous wait during a read access

A[25:0]
NEx
NWAIT
NOE
D[15:0]
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
1343/1422
≥ (
DATAST 4
max_wait_assertion_time
(
≥ ( × )
4 HCLK + max_wait_assertion_time
and Figure 419 show the number of HCLK clock cycles that are added to the
address phase
don't care
Doc ID 018909 Rev 4
× )
HCLK + max_wait_assertion_time
>
address_phase
–
≥ ×
DATAST 4 HCLK
Memory transaction
data setup phase
hold_phase
+
–
address_phase hold_phase
don't care
data driven
by memory
4HCLK
RM0090
)