Otg_Hs Register Map; Table 184. Otg_Hs Register Map And Reset Values - ST STM32F40 Series Reference Manual

RM0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit 31:5 Reserved, must be kept at reset value.
Bit 4 PHYSUSP: PHY suspended
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 GATEHCLK: Gate HCLK
Bit 0 STPPCLK: Stop PHY clock
31.12.6

OTG_HS register map

The table below gives the USB OTG register map and reset values.

Table 184. OTG_HS register map and reset values

Offset Register
OTG_HS_GOT
GCTL
0x000
Reset value
OTG_HS_GOT
GINT
0x004
Reset value
OTG_HS_GAH
BCFG
0x008
Reset value
OTG_HS_GUS
BCFG
0x00C
Reset value 0
OTG_HS_GRS
TCTL
0x010
Reset value 1
Reserved
Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended
after the application has set the STPPCLK bit (bit 0).
The application sets this bit to gate HCLK to modules other than the AHB Slave and Master
and wakeup logic when the USB is suspended or the session is not valid. The application
clears this bit when the USB is resumed or a new session starts.
The application sets this bit to stop the PHY clock when the USB is suspended, the session
is not valid, or the device is disconnected. The application clears this bit when the USB is
resumed or a new session starts.
Reserved
Reserved
Reserved
0 0 0 0 0
0
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
Reserved
0 0 0 1
0 0 0
Reserved
0 0 0 0 0 0 0
Reserved
9 8 7 6 5 4
rw
Reserved
0 0 0 0
Reserved
0 0
0 0
TRDT
Reserved
0 0 1 0 1 0 1
TXFNUM
0 0 0 0 0 0
3 2 1 0
rw rw
0 0
Res.
0
Reserved
0
TOCAL
0 0 0
0 0 0 0 0
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