Nand Flash / Pc Card Supported Memories And Transactions; Timing Diagrams For Nand And Pc Card; Table 219. Supported Memories And Transactions - ST STM32F40 Series Reference Manual

RM0090
32.6.2

NAND Flash / PC Card supported memories and transactions

Table 219
Transactions not allowed (or not supported) by the NAND Flash / PC Card controller appear
in gray.

Table 219. Supported memories and transactions

Device
NAND 8-bit
NAND 16-bit
32.6.3

Timing diagrams for NAND and PC Card

Each PC Card/CompactFlash and NAND Flash memory bank is managed through a set of
registers:
●
Control register: FSMC_PCRx
●
Interrupt status register: FSMC_SRx
●
ECC register: FSMC_ECCRx
●
Timing register for Common memory space: FSMC_PMEMx
●
Timing register for Attribute memory space: FSMC_PATTx
●
Timing register for I/O space: FSMC_PIOx
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access,
plus one parameter that defines the timing for starting driving the databus in the case of a
write. Figure 423
knowing that Attribute and I/O (only for PC Card) memory space access timings are similar.
below shows the supported devices, access modes and transactions.
Mode R/W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
shows the timing parameter definitions for common memory accesses,
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
AHB Memory
data size data size not allowed
8 8
8 8
16 8
16 8
32 8
32 8
8 16
8 16
16 16
16 16
32 16
32 16
Allowed/
Comments
Y
Y
Y Split into 2 FSMC accesses
Y Split into 2 FSMC accesses
Y Split into 4 FSMC accesses
Y Split into 4 FSMC accesses
Y
N
Y
Y
Y Split into 2 FSMC accesses
Y Split into 2 FSMC accesses
1360/1422