Table 202. Fsmc_Bwtrx Bit Fields; Figure 412. Mode C Read Accesses - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)

Table 202. FSMC_BWTRx bit fields

Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Note: The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its
content is don't care.
Mode C - NOR Flash - OE toggling

Figure 412. Mode C read accesses

1335/1422
Bit name
Reserved 0x0
ACCMOD 0x1
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses,
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET
Minimum value for ADDSET is 0.
A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
HCLK cycles
Doc ID 018909 Rev 4
Value to set
Memory transaction
ADDSET
data driven
by memory
DATAST
HCLK cycles
RM0090
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