Figure 414. Mode D Read Accesses; Figure 415. Mode D Write Accesses - ST STM32F40 Series Reference Manual

RM0090
Mode D - asynchronous access with extended address

Figure 414. Mode D read accesses

Figure 415. Mode D write accesses

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
ADDSET
HCLK cycles
A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
ADDSET
HCLK cycles
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
Memory transaction
data driven
by memory
DATAST
HCLK cycles
ADDHLD
HCLK cycles
Memory transaction
1HCLK
data driven by FSMC
(DATAST+ 1)
HCLK cycles
ADDHLD
HCLK cycles
ai15566
ai15567
1338/1422