Table 195. Fsmc_Bcrx Bit Fields; Figure 406. Mode1 Write Accesses - ST STM32F40 Series Reference Manual

RM0090

Figure 406. Mode1 write accesses

The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).

Table 195. FSMC_BCRx bit fields

Bit
number
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
Bit name
Reserved
CBURSTRW
Reserved
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
Memory transaction
ADDSET
HCLK cycles
0x000
0x0 (no effect on asynchronous mode)
0x0
Set to 1 if the memory supports this feature. Otherwise keep at
0.
0x0
0x0 (no effect on asynchronous mode)
0x1
As needed
0x0
Meaningful only if bit 15 is 1
0x0
0x1
Don't care
As needed
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
Value to set
ai15558
1328/1422