Otg_Hs Functional Description; High-Speed Otg Phy; External Full-Speed Otg Phy Using The I2C Interface; Embedded Full-Speed Otg Phy - ST STM32F40 Series Reference Manual

RM0090
31.3

OTG_HS functional description

Figure 381

Figure 381. USB OTG interface block diagram

CPU
Memory
Peripheral 1
Peripheral 2
1. The USB DMA cannot directly address the internal Flash memory.
31.3.1

High-speed OTG PHY

The USB OTG HS core embeds an ULPI interface to connect an external HS phy.
31.3.2

External Full-speed OTG PHY using the I2C interface

The USB OTG HS core embeds an I
31.3.3

Embedded Full-speed OTG PHY

The full-speed OTG PHY includes the following components:
●
FS/LS transceiver module used by both host and Device. It directly drives transmission
and reception on the single-ended USB lines.
● Integrated ID pull-up resistor used to sample the ID line for A/B Device identification.
●
DP/DM integrated pull-up and pull-down resistors controlled by the OTG_HS core
depending on the current role of the device. As a peripheral, it enables the DP pull-up
resistor to signal full-speed peripheral connections as soon as V
a valid level (B-session valid). In host mode, pull-down resistors are enabled on both
shows the OTG_HS interface block diagram.
AHB master interface
Interrupt
AHB slave interface
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
USB OTG HS core
Data FIFO
single-port RAM
(SPRAM)
2
C interface allowing to connect an external FS phy.
ULPI PHY
ULPI interface
2.0 USB
is sensed to be at
BUS
1162/1422
ai17107b