Otg_Hs Control And Status Registers; Figure 383. Interrupt Hierarchy - ST STM32F40 Series Reference Manual

USB on-the-go high-speed (OTG_HS)

Figure 383. Interrupt hierarchy

31 30 29 28 27 26 25 24 23 22 21 20 19 18
Core interrupt
(1)
register
Interrupt
sources
Host port control and status
Host all channels interrupt
Host channels interrupt
registers 0 to 11
1. The core interrupt register bits are shown in
31.12

OTG_HS control and status registers

By reading from and writing to the control and status registers (CSRs) through the AHB
slave interface, the application controls the OTG_HS controller. These registers are 32 bits
1177/1422
17:10 9 8
Device all endpoints
interrupt register
21:16 5:0
OUT endpoints IN endpoints
Device IN/OUT endpoint
interrupt registers 0 to 5
register
register
OTG_HS core interrupt register (OTG_HS_GINTSTS) on page
Doc ID 018909 Rev 4
AND
7:3 2 1 0
Core interrupt mask
OTG
interrupt
register
Device all endpoints
interrupt mask register
Device IN/OUT
Device each IN/OUT endpoint
endpoints common
interrupt mask register
interrupt mask register
Host all channels
interrupt mask register
Host channels interrupt
mask registers 0 to 11
Interrupt
AND
OR
Global interrupt
mask (Bit 0)
AHB configuration
register
register
Device each endpoint
interrupt register
31:16 15:0
EP1OUT EP1IN
RM0090
OR
endp_multi_proc_intrpt
endp_interrupt[31:0]
Device each endpoint
interrupt mask register
ai16093b
1194.