Flexible Static Memory Controller (Fsmc); Fsmc Main Features - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)

32 Flexible static memory controller (FSMC)
This section applies to the whole STM32F4xx family devices, unless otherwise specified.
32.1

FSMC main features

The FSMC block is able to interface with synchronous and asynchronous memories and 16-
bit PC memory cards. Its main purpose is to:
●
Translate the AHB transactions into the appropriate external device protocol
● Meet the access timing requirements of the external devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique chip select. The FSMC performs
only one access at a time to an external device.
The FSMC has the following main features:
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Interfaces with static memory-mapped devices including:
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● Two banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data
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16-bit PC Card compatible devices
● Supports burst mode access to synchronous devices (NOR Flash and PSRAM)
●
8- or 16-bit wide databus
● Independent chip select control for each memory bank
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Independent configuration for each memory bank
● Programmable timings to support a wide range of devices, in particular:
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Write enable and byte lane select outputs for use with PSRAM and SRAM devices
● Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to
external 16-bit or 8-bit devices
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A Write FIFO, 2-word long (16-word long for STM32F42x and STM32F43x), each word
is 32 bits wide, only stores data and not the address. Therefore, this FIFO only buffers
AHB write burst transactions. This makes it possible to write to slow memories and free
the AHB quickly for other operations. Only one burst at a time is buffered: if a new AHB
burst or single transaction occurs while an operation is in progress, the FIFO is drained.
The FSMC will insert wait states until the current memory access is complete).
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External asynchronous wait control
1317/1422
Static random access memory (SRAM)
Read-only memory (ROM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
Programmable wait states (up to 15)
Programmable bus turnaround cycles (up to 15)
Programmable output enable and write enable delays (up to 15)
Independent read and write timings and protocol, so as to support the widest
variety of memories and timings
Doc ID 018909 Rev 4
RM0090