Mechanism To Select The Jtag-Dp Or The Sw-Dp; Pinout And Debug Port Pins; Figure 426. Swj Debug Port - ST STM32F40 Series Reference Manual

Debug support (DBG)

Figure 426. SWJ debug port

JTMS/SWDIO
JTCK/SWCLK
Figure 426
TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.
33.3.1

Mechanism to select the JTAG-DP or the SW-DP

By default, the JTAG-Debug Port is active.
If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG
sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the
JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only
the SWCLK and SWDIO pins.
This sequence is:
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted
first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1
33.4

Pinout and debug port pins

The STM32F4xx MCUs are available in various packages with different numbers of
available pins. As a result, some functionality (ETM) related to pin availability may differ
between packages.
1377/1422
TRACESWO
SWJ-DP
JTDO TDO
TDI
JTDI
nTRST
NJTRST
SWDITMS
SWDO
SWDOEN
SWCLKTCK
shows that the asynchronous TRACE output (TRACESWO) is multiplexed with
Doc ID 018909 Rev 4
(asynchronous trace)
SWD/JTAG
select
TDO
TDI
nTRST
JTAG-DP
TCK
TMS
nPOTRST
nPOTRST
DBGRESETn
DBGDI
DBGDO
SW-DP
DBGDOEN
DBGCLK
RM0090
From
power-on
reset
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