Otg_Hs Global Registers - ST STM32F40 Series Reference Manual

RM0090
31.12.2

OTG_HS global registers

These registers are available in both host and peripheral modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
OTG_HS control and status register (OTG_HS_GOTGCTL)
Address offset: 0x000
Reset value: 0x0000 0800
The OTG control and status register controls the behavior and reflects the status of the OTG
function of the core.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 BSVLD: B-session valid
Indicates the peripheral mode transceiver status.
0: B-session is not valid.
1: B-session is valid.
In OTG mode, you can use this bit to determine if the device is connected or disconnected.
Note: Only accessible in peripheral mode.
Bit 18 ASVLD: A-session valid
Indicates the host mode transceiver status.
0: A-session is not valid
1: A-session is valid
Note: Only accessible in host mode.
Bit 17 DBCT: Long/short debounce time
Indicates the debounce time of a detected connection.
0: Long debounce time, used for physical connections (100 ms + 2.5 µs)
1: Short debounce time, used for soft connections (2.5 µs)
Note: Only accessible in host mode.
Bit 16 CIDSTS: Connector ID status
Indicates the connector ID status on a connect event.
0: The OTG_HS controller is in A-device mode
1: The OTG_HS controller is in B-device mode
Note: Accessible in both peripheral and host modes.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 DHNPEN: Device HNP enabled
The application sets this bit when it successfully receives a SetFeature.SetHNPEnable
command from the connected USB host.
0: HNP is not enabled in the application
1: HNP is enabled in the application
Note: Only accessible in peripheral mode.
Reserved
r r r r
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
9 8 7 6
Reserved
rw rw rw r
5 4 3 2 1 0
rw r
1184/1422