Csr Memory Map; Table 178. Core Global Control And Status Registers (Csrs); Figure 384. Csr Memory Map - ST STM32F40 Series Reference Manual

USB on-the-go high-speed (OTG_HS)
31.12.1

CSR memory map

The host and peripheral mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.

Figure 384. CSR memory map

1. x = 5 in peripheral mode and x = 11 in host mode.
Global CSR map
These registers are available in both host and peripheral modes.

Table 178. Core global control and status registers (CSRs)

Acronym
OTG_HS_GOTGCTL
OTG_HS_GOTGINT
OTG_HS_GAHBCFG
OTG_HS_GUSBCFG
OTG_HS_GRSTCTL
1179/1422
0000h
0400h
0800h
Device mode CSRs (1.5 Kbyte)
0E00h
Power and clock gating CSRs (0.5 Kbyte)
1000h
Device EP 0/Host channel 0 FIFO (4 Kbyte)
2000h
Device EP1/Host channel 1 FIFO (4 Kbyte)
3000h
Device EP (x – 1)
Device EP x
2 0000h
Direct access to data FIFO RAM
for debugging (128 Kbyte)
3 FFFFh
Address
offset
0x000 OTG_HS control and status register (OTG_HS_GOTGCTL) on page 1184
0x004 OTG_HS interrupt register (OTG_HS_GOTGINT) on page 1186
0x008 OTG_HS AHB configuration register (OTG_HS_GAHBCFG) on page 1187
0x00C OTG_HS USB configuration register (OTG_HS_GUSBCFG) on page 1188
0x010 OTG_HS reset register (OTG_HS_GRSTCTL) on page 1191
Doc ID 018909 Rev 4
Core global CSRs (1 Kbyte)
Host mode CSRs (1 Kbyte)
(1) (1)
/Host channel (x – 1)
(1) (1)
/Host channel x FIFO (4 Kbyte)
Reserved
Register name
DFIFO
push/pop
to this region
FIFO (4 Kbyte)
DFIFO
debug read/
write to this
region
RM0090
ai15615b