Nand/Pc Card Address Mapping; Table 185. Nor/Psram Bank Selection; Table 186. External Memory Address; Table 187. Memory Mapping And Timing Registers - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)

Table 185. NOR/PSRAM bank selection

00
01
10
11
1. HADDR are internal AHB address lines that are translated to external memory.
HADDR[25:0] contain the external memory address. Since HADDR is a byte address
whereas the memory is addressed in words, the address actually issued to the memory
varies according to the memory data width, as shown in the following table.

Table 186. External memory address

Memory width
8-bit
16-bit
1. In case of a 16-bit external memory width, the FSMC will internally use HADDR[25:1] to generate the
address for external memory FSMC_A[24:0].
Whatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory
address A[0].
Wrap support for NOR Flash/PSRAM
Wrap burst mode for synchronous memories is not supported. The memories must be
configured in linear burst mode of undefined length.
32.4.2

NAND/PC Card address mapping

In this case, three banks are available, each of them divided into memory spaces as
indicated in

Table 187. Memory mapping and timing registers

Start address
0x9C00 0000
0x9800 0000
0x9000 0000
0x8800 0000
0x8000 0000
0x7800 0000
0x7000 0000
1321/1422
(1)
HADDR[27:26]
(1)
Data address issued to the memory
HADDR[25:0]
HADDR[25:1] >> 1
Table 187.
End address
0x9FFF FFFF
0x9BFF FFFF Bank 4 - PC card
0x93FF FFFF
0x8BFF FFFF
Bank 3 - NAND Flash
0x83FF FFFF
0x7BFF FFFF
Bank 2- NAND Flash
0x73FF FFFF
Doc ID 018909 Rev 4
Bank 1 NOR/PSRAM 1
Bank 1 NOR/PSRAM 2
Bank 1 NOR/PSRAM 3
Bank 1 NOR/PSRAM 4
FSMC Bank Memory space
Attribute
Common
Attribute
Common
Attribute
Common
Selected bank
Maximum memory capacity (bits)
64 Mbytes x 8 = 512 Mbit
64 Mbytes/2 x 16 = 512 Mbit
Timing register
I/O FSMC_PIO4 (0xB0)
FSMC_PATT4 (0xAC)
FSMC_PMEM4 (0xA8)
FSMC_PATT3 (0x8C)
FSMC_PMEM3 (0x88)
FSMC_PATT2 (0x6C)
FSMC_PMEM2 (0x68)
RM0090