ST STM32F423RH Manuals
Manuals and User Guides for ST STM32F423RH. We have 1 ST STM32F423RH manual available for free PDF download: Reference Manual
ST STM32F423RH Reference Manual (1324 pages)
advanced Arm-based 32-bit MCUs
Brand: ST
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Category: Microcontrollers
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Size: 15 MB
Table of Contents
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Glossary53
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I-Bus55
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D-Bus55
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S-Bus55
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Busmatrix56
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Introduction57
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Bit Banding62
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Introduction66
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Erase72
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Programming73
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Interrupts74
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Option Bytes74
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Low-Power Modes100
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Sleep Mode103
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Stop Mode105
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Standby Mode108
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PWR Register Map116
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Reset117
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System Reset117
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Power Reset118
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Clocks119
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HSE Clock121
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HSI Clock122
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LSE Clock123
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LSI Clock124
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RTC/AWU Clock125
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Watchdog Clock125
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RCC Registers129
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For Stm32F413Xx140
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For Stm32F423Xx141
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For Stm32F413Xx151
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For Stm32F423Xx152
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RCC Register Map181
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Port Pins194
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GPIO Registers196
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(X = a196
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(X = a197
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(X = a199
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(X = a201
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SYSCFG Registers204
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(Syscfg_Exticr1)206
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(Syscfg_Exticr2)206
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(Syscfg_Exticr3)207
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(Syscfg_Exticr4)208
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DMA Introduction214
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DMA Overview216
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DMA Transactions217
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Arbiter219
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DMA Streams219
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Circular Mode223
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Fifo226
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Flow Controller230
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Error Management233
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DMA Interrupts234
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DMA Registers235
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DMA Register Map245
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NVIC Features249
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EXTI Registers258
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AHB Interface266
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Introduction307
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QUADSPI Pins308
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QUADSPI Usage317
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Ncs Behavior320
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ADC Introduction336
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ADC Clock338
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Timing Diagram340
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Analog Watchdog340
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Scan Mode341
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Data Alignment343
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Data Management347
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Using the DMA347
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ADC Interrupts350
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ADC Registers351
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DAC Introduction366
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DAC Data Format368
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DAC Conversion369
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DMA Request371
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Noise Generation371
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DAC Registers378
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(Dac_Dhr12L1)382
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(Dac_Dhr12L2)383
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(Dac_Dhr12Ld)384
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(Dac_Dhr8Rd)385
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DAC Register Map386
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Introduction388
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Integrator Unit411
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Analog Watchdog411
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Extreme Detector414
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Data Unit Block415
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DFSDM Interrupts418
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(Dfsdm_Fltxawsr)437
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Introduction450
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RNG Operation454
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RNG Clocking455
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Error Management455
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RNG Interrupts456
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Introduction457
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Data Collection457
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RNG Registers458
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RNG Register Map461
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Time-Base Unit464
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Counter Modes466
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Clock Selection478
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PWM Input Mode485
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PWM Mode487
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One-Pulse Mode497
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Debug Mode506
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Time-Base Unit535
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Counter Modes537
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Clock Selection546
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PWM Input Mode552
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PWM Mode555
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One-Pulse Mode558
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Debug Mode571
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Time-Base Unit598
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Counter Modes600
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Clock Selection603
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PWM Mode610
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One-Pulse Mode611
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Debug Mode616
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(Timx_Ccmr1)634
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(Timx_Ccer)637
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Introduction642
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Time-Base Unit643
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Counting Mode645
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Clock Source648
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Debug Mode649
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TIM6/7 Registers650
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Introduction655
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Glitch Filter657
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Prescaler658
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Operating Mode659
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Timeout Function661
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Register Update662
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Counter Mode663
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Timer Enable663
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Encoder Mode664
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Debug Mode665
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LPTIM Interrupts665
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LPTIM Registers666
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Debug Mode679
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IWDG Registers680
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Debug Mode687
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WWDG Registers688
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Introduction691
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AES Interrupts729
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AES Registers731
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AES Register Map742
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Introduction744
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Tamper Detection756
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Alarm Output758
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RTC Interrupts759
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RTC Registers760
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(Rtc_Tafcr)775
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RTC Register Map779
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Introduction782
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Mode Selection785
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Software Reset790
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Data Transfer791
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Smbus Slave Mode820
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Error Conditions827
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DMA Requests829
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Debug Mode830
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FMPI2C Registers831
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Mode Selection850
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I2C Slave Mode851
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I2C Master Mode854
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Error Conditions860
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Smbus862
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DMA Requests865
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I 2 C Interrupts867
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I 2 C Debug Mode869
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I 2 C Registers869
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I2C Register Map882
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Transmitter889
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Receiver892
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Parity Control909
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Smartcard915
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USART Interrupts923
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USART Registers924
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Introduction935
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I2S Features937
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SPI Status Flags953
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SPI Error Flags954
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TI Mode955
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CRC Calculation956
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SPI Interrupts958
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Figure 330. I959
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I2S Full-Duplex960
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Figure 336. I963
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Clock Generator967
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I 2 S Slave Mode972
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I 2 S Interrupts975
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DMA Features975
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Table 177. I975
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Mode981
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SPI Register Map986
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Introduction987
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Main Features988
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Main SAI Modes990
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Audio Data Size991
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Frame Length992
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FS Signal Role993
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Internal Fifos997
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Specific Features1000
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Mute Mode1001
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MONO/STEREO Function1001
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Companding Mode1002
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Error Flags1005
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Interrupt Sources1008
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Disabling the SAI1009
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SAI DMA Interface1010
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SAI Registers1011
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SAI Register Map1024
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SDIO Main Features1026
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SDIO Bus Topology1026
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SDIO Adapter1030
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SDIO APB2 Interface1041
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Card Reset1043
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Block Write1044
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Block Read1045
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Card Status Register1051
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SD Status Register1054
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Table 192. SD Status1054
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SD I/O Mode1058
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Response Formats1062
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Table 204. Lock Card1062
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R1B1063
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R3 (OCR Register)1064
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R4 (Fast I/O)1064
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R4B1064
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SDIO Interrupts1067
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HW Flow Control1067
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SDIO Registers1068
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SDIO Response 11071
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SDIO Register Map1083
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Introduction1085
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Bxcan Main Features1085
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CAN 2.0B Active Core1086
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Tx Mailboxes1087
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Acceptance Filters1087
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Initialization Mode1089
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Normal Mode1090
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Test Mode1091
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Silent Mode1091
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Loop Back Mode1092
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Reception Handling1095
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Identifier Filtering1096
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Message Storage1100
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Error Management1102
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Bit Timing1102
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Bxcan Interrupts1105
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CAN Registers1106
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CAN Filter Registers1123
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Bxcan Register Map1127
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Introduction1131
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OTG Main Features1132
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General Features1132
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Host-Mode Features1133
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Split Rail for USB1133
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OTG Implementation1134
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OTG Block Diagram1135
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OTG Core1136
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Full-Speed OTG PHY1136
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ID Line Detection1137
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HNP Dual Role Device1138
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SRP Dual Role Device1138
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USB Peripheral1138
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Peripheral States1139
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Peripheral Endpoints1140
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USB Host1142
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SRP-Capable Host1143
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USB Host States1143
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Host Channels1145
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Host Scheduler1146
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SOF Trigger1147
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Host Sofs1147
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Peripheral Sofs1147
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OTG Low-Power Modes1148
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USB Data Fifos1149
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FIFO RAM Allocation1152
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OTG_FS Interrupts1154
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CSR Memory Map1156
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OTG_FS Registers1160
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(Otg_Dieptxf0)1180
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(Otg_Hnptxsts)1181
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(Otg_Hptxfsiz)1188
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FIFO Number)1188
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(Otg_Hfnum)1191
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(Otg_Hptxsts)1191
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(Otg_Haintmsk)1193
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(X = 01196
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(X = 01197
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(X = 01198
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(X = 01199
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(Otg_Diepmsk)1205
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(Otg_Doepmsk)1206
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(Otg_Daintmsk)1208
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OTG Device1208
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(Otg_Dvbusdis)1208
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OTG Device1209
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(Otg_Dvbuspulse)1209
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(Otg_Diepempmsk)1209
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(Otg_Diepctl0)1210
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(X = 11211
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(X = 01214
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(Otg_Dieptsiz0)1215
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Endpoint Number)1216
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(X = 11217
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(Otg_Doepctl0)1218
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(X = 01219
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(Otg_Doeptsiz0)1221
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(X = 11222
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Core Initialization1234
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Host Initialization1234
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Debug Support (DBG)1284
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Overview1284
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SWJ Debug Port Pins1287
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JTAG TAP Connection1289
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MCU Device ID Code1291
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Boundary Scan TAP1291
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JTAG Debug Port1292
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SW Debug Port1294
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SW Protocol Sequence1294
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SW-DP Registers1296
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SW-AP Registers1297
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Core Debug1298
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General Description1300
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General Description1302
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Main ETM Registers1302
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Introduction1307
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TRACE Pin Assignment1309
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TPUI Formatter1310
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Synchronous Mode1311
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Asynchronous Mode1312
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TPIU Registers1312
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DBG Register Map1314
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Flash Size1316
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Revision History1318
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