Ahb Interface; Supported Memories And Transactions - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)
32.3

AHB interface

The AHB slave interface enables internal CPUs and other bus master peripherals to access
the external static memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The Chip Select toggles for each access.
The FSMC generates an AHB error in the following conditions:
● When reading or writing to an FSMC bank which is not enabled
●
When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the
FSMC_BCRx register.
●
When reading or writing to the PC Card banks while the input pin FSMC_CD (Card
Presence Detection) is low.
The effect of this AHB error depends on the AHB master which has attempted the R/W
access:
●
If it is the Cortex™-M4F CPU, a hard fault interrupt is generated
●
If is a DMA, a DMA transfer error is generated and the corresponding DMA channel is
automatically disabled.
The AHB clock (HCLK) is the reference clock for the FSMC.
32.3.1

Supported memories and transactions

General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
●
AHB transaction size and memory data size are equal
There is no issue in this case.
●
AHB transaction size is greater than the memory size
In this case, the FSMC splits the AHB transaction into smaller consecutive memory
accesses in order to meet the external data width.
●
AHB transaction size is smaller than the memory size
Asynchronous transfers may or not be consistent depending on the type of external
device.
–
–
1319/1422
Asynchronous accesses to devices that have the byte select feature (SRAM,
ROM, PSRAM).
a) FSMC allows write transactions accessing the right data through its byte lanes
NBL[1:0]
b) Read transactions are allowed. All memory bytes are read and the useless
ones are discarded. The NBL[1:0] are kept low during read transactions.
Asynchronous accesses to devices that do not have the byte select feature (NOR
and NAND Flash 16-bit).
This situation occurs when a byte access is requested to a 16-bit wide Flash
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