Table 197. Fsmc_Bcrx Bit Fields; Table 198. Fsmc_Btrx Bit Fields - ST STM32F40 Series Reference Manual

Flexible static memory controller (FSMC)
The differences compared with mode1 are the toggling of NOE and the independent read
and write timings.

Table 197. FSMC_BCRx bit fields

Bit
number
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0

Table 198. FSMC_BTRx bit fields

Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
1331/1422
Bit name
Reserved 0x000
CBURSTRW 0x0 (no effect on asynchronous mode)
Reserved 0x0
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD 0x1
WAITEN 0x0 (no effect on asynchronous mode)
WREN 0x1
WAITCFG As needed
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
MTYP As needed, exclude 0x2 (NOR Flash)
MUXEN 0x0
MBKEN 0x1
Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses, DATAST HCLK cycles for read accesses).
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET
Minimum value for ADDSET is 0.
Doc ID 018909 Rev 4
Value to set
Value to set
RM0090