Table 199. Fsmc_Bwtrx Bit Fields; Figure 409. Mode2 And Mode B Read Accesses - ST STM32F40 Series Reference Manual

RM0090

Table 199. FSMC_BWTRx bit fields

Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Mode 2/B - NOR Flash

Figure 409. Mode2 and mode B read accesses

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses,
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET
Minimum value for ADDSET is 0.
A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
HCLK cycles
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
Value to set
Memory transaction
ADDSET
data driven
by memory
DATAST
HCLK cycles
ai15561
1332/1422