Figure 542. Usart Example Of Synchronous Master Transmission; Figure 543. Usart Data Clock Timing Diagram In Synchronous Master Mode; (M Bits =00) - ST STM32G4 Series Reference Manual

RM0440
Note: In master mode, the SCLK pin operates in conjunction with the TX pin. Thus, the clock is
provided only if the transmitter is enabled (TE=1) and data are being transmitted
(USART_TDR data register written). This means that it is not possible to receive
synchronous data without transmitting data.

Figure 543. USART data clock timing diagram in synchronous master mode

Idle or preceding
transmission
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Data on TX
(from master)
Data on RX
(from slave)
Capture strobe
Universal synchronous/asynchronous receiver transmitter (USART/UART)

Figure 542. USART example of synchronous master transmission

USART
Start
0
LSB
Start
0
LSB
RX
TX
SCLK

(M bits =00)

M bits = 00 (8 data bits)
1 2 3 4
1 2 3 4
RM0440 Rev 4
Data out
Data in
Synchronous device
(e.g. slave SPI)
Clock
Stop
*
*
*
*
5 6 7
Stop
MSB
5 6 7
MSB
*
*LBCL bit controls last data pulse
MSv31158V1
Idle or next
transmission
MSv34709V2
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