Usart Synchronous Mode; Figure 253. Break Detection In Lin Mode Vs. Framing Error Detection - ST STM32F100 Series Reference Manual

RM0041
Case 1: break occurring after an Idle
RX line
RXNE /FE
LBDF
Case 2: break occurring while data is being received
RX line
RXNE /FE
LBDF
23.3.9

USART synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
•
LINEN bit in the USART_CR2 register,
•
SCEN, HDSEL and IREN bits in the USART_CR3 register.
The USART allows the user to control a bidirectional synchronous serial communications in
master mode. The CK pin is the output of the USART transmitter clock. No clock pulses are
sent to the CK pin during start bit and stop bit. Depending on the state of the LBCL bit in the
USART_CR2 register clock pulses are generated or not during the last valid data bit
(address mark). The CPOL bit in the USART_CR2 register allows the user to select the
clock polarity, and the CPHA bit in the USART_CR2 register allows the user to select the
phase of the external clock (see
During the Idle state, preamble and send break, the external CK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as CK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending
on CPOL and CPHA), without any oversampling. A setup and a hold time must be
respected (which depends on the baud rate: 1/16 bit time).
Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR
Universal synchronous asynchronous receiver transmitter (USART)

Figure 253. Break detection in LIN mode vs. Framing error detection

data 1 IDLE
data 1 data2
1 data time
BREAK
1 data time
BREAK
Figure 254, Figure 255
RM0041 Rev 6
data 2 (0x55) data 3 (header)
1 data time
data 2 (0x55) data 3 (header)
1 data time
& Figure 256).
MSv31157V1
623/709
646