Clock Generator; Figure 336. Audio Sampling Frequency Definition; Figure 337. I - ST STM32F446 Series Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in
slave mode.
26.6.4

Clock generator

2
The I S bitrate determines the data flow on the I
frequency.
2
I S bitrate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I
2
I S bitrate = 16 × 2 × f
It will be: I
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 337
system clock.
1. Where x = 2.
878/1328
S
2
S bitrate = 32 x 2 x f
S

Figure 336. Audio sampling frequency definition

presents the communication clock architecture. The I2Sx clock is always the

Figure 337. I

2
S data line and the I
2
S bitrate is calculated as follows:
if the packet length is 32-bit wide.
2
S clock generator architecture
RM0390 Rev 4
RM0390
2
S clock signal