I2S Clock Generator; Figure 2. I2S Clock Generator Architecture - ST STM32F0 Series Application Note

AN4055
2.2.3

I2S clock generator

This section describes the I2S clock generator. It is dependent on:
●
Master clock MCLK (enable or disable)
● Frame width
●
I2S peripheral clock (I2SCLK).
Figure 2.
I2SxCLK
The audio sampling frequency may be 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz. To reach the desired frequency, the linear divider
(DIV) needs to be programmed according to the formulas below:
When the master clock is generated (MCKOE bit in the SPI_I2SPR register is set):
●
FS = I2SxCLK/[(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16 bits wide
●
FS = I2SxCLK/[(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32 bits wide
Where ODD is an odd factor for the prescaler.
When the master clock is disabled (MCKOE bit cleared):
●
FS = I2SxCLK/[(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16 bits wide
● FS = I2SxCLK/[(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32 bits wide
Note: This tool does not configure the I2S register.
The sampling frequency error is computed as an indicator according to the I2S parameters
which are not configured in the output file "system_stm32f0xx.c".
I2S clock generator architecture
8-bit linear
divider +
reshaping stage
I2SDIV[7:0]
MCKOE ODD
Doc ID 022837 Rev 1
Div2
Divider by 4
I2SMOD
Getting started
MCK
0
CK
0
1
1
MCKOE
CHLEN
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