Dma Registers; Dma Low Interrupt Status Register (Dma_Lisr) - ST STM32F412 Reference Manual

RM0402
9.5

DMA registers

The DMA registers have to be accessed by words (32 bits).
9.5.1

DMA low interrupt status register (DMA_LISR)

Address offset: 0x000
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: stream x transfer complete interrupt flag (x = 3 to 0)
Bits 26, 20, 10, 4 HTIFx: stream x half transfer interrupt flag (x = 3 to 0)
Bits 25, 19, 9, 3 TEIFx: stream x transfer error interrupt flag (x = 3 to 0)
Bits 24, 18, 8, 2 DMEIFx: stream x direct mode error interrupt flag (x = 3 to 0)
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: stream x FIFO error interrupt flag (x = 3 to 0)
27 26 25
TCIF3 HTIF3 TEIF3
r r r
11 10 9
TCIF1 HTIF1 TEIF1
r r r
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no transfer complete event on stream x
1: a transfer complete event occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no half transfer event on stream x
1: a half transfer event occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no transfer error on stream x
1: a transfer error occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No direct mode error on stream x
1: a direct mode error occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no FIFO error event on stream x
1: a FIFO error event occurred on stream x
Direct memory access controller (DMA)
24 23 22
DMEIF3 Res. FEIF3 TCIF2
r r
8 7 6
DMEIF1 Res. FEIF1 TCIF0
r r
RM0402 Rev 6
21 20 19 18
HTIF2 TEIF2 DMEIF2
r r r r
5 4 3 2
HTIF0 TEIF0 DMEIF0
r r r r
17 16
Res. FEIF2
r
1 0
Res. FEIF0
r
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