Dma Registers; Dma Low Interrupt Status Register (Dma_Lisr) - ST STM32F207 Series Reference Manual

DMA controller (DMA)
9.5

DMA registers

The DMA registers have to be accessed by words (32 bits).
9.5.1

DMA low interrupt status register (DMA_LISR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28
Reserved
r r r r
15 14 13 12
Reserved
r r r r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3..0)
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=3..0)
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=3..0)
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=3..0)
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=3..0)
198/1381
27 26 25
TCIF3 HTIF3 TEIF3
r r r
11 10 9
TCIF1 HTIF1 TEIF1
r r r
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No Direct Mode Error on stream x
1: A Direct Mode Error occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No FIFO Error event on stream x
1: A FIFO Error event occurred on stream x
24 23 22
DMEIF3 Reserv FEIF3 TCIF2
ed
r r
8 7 6
DMEIF1 Reserv FEIF1 TCIF0
ed
r r
RM0033 Rev 9
21 20 19 18
HTIF2 TEIF2 DMEIF2 Reserv
r r r r
5 4 3 2
HTIF0 TEIF0 DMEIF0 Reserv
r r r r
RM0033
17 16
FEIF2
ed
r
1 0
FEIF0
ed
r