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M30245 Group
2.8.5 USB Operation (Endpoint 0)
Endpoint 0 is used only for control transfer.
Endpoint 0 FIFO consists of total 256 bytes including IN (transmit) FIFO and OUT (receive) FIFO each
respectively of 128 bytes. The starting position is allocated from the 3072nd byte to the 3327th byte of the
endpoint FIFO. Both the endpoint 0 FIFO size and the starting position are fixed. The FIFO size to be
used is determined by the USB endpoint 0 maximum packet size.
The packet data received from the host CPU are written in endpoint 0 OUT FIFO. When a data receive
request is issued by the host CPU while data already exists in the OUT FIFO, responds with NAK auto-
matically. When packet data are transmitted to the host CPU, the transmit data are written in the endpoint
0 IN FIFO. When a data transmit request is issued by the host CPU before the data are written in IN FIFO,
responds with NAK automatically. A packet data can realize higher transmit/receive by enabling continu-
ous transfer.
When an error is detected in control transfer, responds with STALL automatically and the error detection
is reported. Based on the status of the endpoint 0 communication, data transmit/receive is controlled in
accordance with the device request which is received from the host CPU.
(1) Related Registers
USB address register
USB address register maintains 7 bits addresses of the USB function control unit that are allocated by
the host CPU. The USB function control unit of the M30245 group responds to the token packet for the
address retained in this register.
When the USB function control unit is in the initial state or has received a reset signal from the host
CPU, this register value is the default address "0000
of USB control register is set to "0"), this register value is the address "0000
After receiving the SET_ADDRESS request from the host CPU, rewrite USB address register and
update the address.
For rewriting USB address register, follow the procedure below:
• When the device is in the default state (USB address register value is "0000
1: When USB address register has received the SET_ADDRESS request from the host CPU, store
the new address data in the USB address register.
2: When the status phase of the SET_ADDRESS request is completed , USB address register is
automatically rewritten into the address written in above-mentioned 1:. When the status phase is
not normally completed, USB address register is not rewritten.
• When the device is in the address state (USB address register value is other than "0000
1: When USB address register has received the SET_ADDRESS request from the host CPU, con-
firm that the status phase of SET_ADDRESS request completes.
2: Store the new address data in USB address register. USB address register is rewritten into the
new address data.
The configuration of USB address register is shown in Figure 2.8.31.
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
page 169 of 354
". When the USB block has been disabled (bit 7
16
2. USB function
".
16
"):
16
"):
16
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