Tim15 Capture/Compare Register 2 (Tim15_Ccr2); Tim15 Break And Dead-Time Register (Tim15_Bdtr) - ST STM32F100 Series Reference Manual

RM0041
15.5.14

TIM15 capture/compare register 2 (TIM15_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
15.5.15

TIM15 break and dead-time register (TIM15_BDTR)

Address offset: 0x44
Reset value: 0x0000
15 14 13
MOE AOE BKP BKE
rw rw rw
Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
12 11 10 9
rw rw rw rw
12 11 10 9
OSSR OSSI LOCK[1:0]
rw rw rw rw
General-purpose timers (TIM15/16/17)
8 7 6
CCR2[15:0]
rw rw rw
8 7 6
rw rw rw
RM0041 Rev 6
5 4 3 2
rw rw rw rw
5 4 3 2
DTG[7:0]
rw rw rw rw
1 0
rw rw
1 0
rw rw
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