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H8/3006, H8/3007

HD6413006, HD6413007

Hardware Manual

ADE-602-145C

Rev. 4.0

1/29/00

Hitachi, Ltd.

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Summary of Contents for Hitachi H8/3006

Page 1 H8/3006, H8/3007 HD6413006, HD6413007 Hardware Manual ADE-602-145C Rev. 4.0 1/29/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 With these features, the H8/3006 and H8/3007 offers easy implementation of compact, high- performance systems. This manual describes the H8/3006 and H8/3007 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.
Page 4 List of Items Revised or Added for This Version Page Item Description 1.1 Overview Specification description Table 1-1 Feature Watchdog timer (WDT) amended 2.6.1 Instruction Set Overview Number of instruction types amended Table 2-7 Bit Manipulation Instructions Function description added 2.6.5 Notes on Use of Bit Manipulation Instruction Description added Explanation...
Page 5 Page Item Description 8.5.2 Register Configuration Description amended Port 8 Data Register (P8DR) 8.6.2 Register Configuration Description amended Port 9 Data Direction Register (P9DDR) 8.7.2 Register Configuration Description amended Port A Data Direction Register (PADDR) Figure 8.7 Port B Pin Configuration Description added 8.8.2 Register Configuration Description amended...
Page 6 Page Item Description B.2 Functions Note deleted P8DDR—Port 8 Data Direction Register B.2 Functions Description amended TSTR—Timer Start Register B.2 Functions Description amended TSNC—Timer Syncro Register B.2 Functions Description amended TMDR—Timer Mode Register B.2 Functions Description amended TISRA—Timer Interrupt Status Register A B.2 Function Description amended TISRB—Timer Interrupt Status Register B...
Page 7 Page Item Description B.2 Functions Register names changed, 8TCSR2—Timer Control/Status Register 2 description amended 8TCSR3—Timer Control/Status Register 3 B.2 Functions Register name changed 8TCNT2—Timer Counter 2 8TCNT3—Timer Counter 3 B.2 Functions Description amended P6DR—Port 6 Data Register Figure C.1 Port 4 Block Diagram Figure amended 730 to 732 Figure C.2(a) to Figure C.2(c)
Page 8: Table Of Contents
Contents Section 1 Overview ......................Overview..........................Internal Block Diagram...................... Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ......................1.3.3 Pin Assignments in Each Mode................13 Section 2 CPU ........................17 Overview..........................17 2.1.1 Features ......................... 17 2.1.2 Differences from H8/300 CPU ................18 CPU Operating Modes .......................
Page 9 Basic Operational Timing ....................53 2.9.1 Overview....................... 53 2.9.2 On-Chip Memory Access Timing ................ 53 2.9.3 On-Chip Supporting Module Access Timing ............54 2.9.4 Access to External Address Space................ 55 Section 3 MCU Operating Modes ................... 57 Overview..........................57 3.1.1 Operating Mode Selection ..................
Page 10 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ..........81 5.2.3 IRQ Status Register (ISR) ..................88 5.2.4 IRQ Enable Register (IER) ................... 89 5.2.5 IRQ Sense Control Register (ISCR) ..............90 Interrupt Sources........................ 91 5.3.1 External Interrupts ....................91 5.3.2 Internal Interrupts....................
Page 11 6.4.3 Valid Strobes......................133 6.4.4 Memory Areas ...................... 134 6.4.5 Basic Bus Control Signal Timing ................. 136 6.4.6 Wait Control......................143 DRAM Interface ........................ 145 6.5.1 Overview....................... 145 DRAM Space and RAS Output Pin Settings............145 6.5.2 6.5.3 Address Multiplexing.................... 146 6.5.4 Data Bus........................
Page 12 7.2.2 I/O Address Registers (IOAR)................189 7.2.3 Execute Transfer Count Registers (ETCR) ............189 7.2.4 Data Transfer Control Registers (DTCR) ............. 191 Register Descriptions (2) (Full Address Mode) ..............194 7.3.1 Memory Address Registers (MAR)..............194 7.3.2 I/O Address Registers (IOAR)................194 7.3.3 Execute Transfer Count Registers (ETCR) ............
Page 13 Port 7..........................251 8.4.1 Overview....................... 251 8.4.2 Register Configuration..................252 Port 8..........................253 8.5.1 Overview....................... 253 8.5.2 Register Configuration..................254 Port 9..........................257 8.6.1 Overview....................... 257 8.6.2 Register Configuration..................258 Port A ..........................261 8.7.1 Overview....................... 261 8.7.2 Register Configuration..................263 Port B ..........................
Page 14 9.4.6 Setting Initial Value of 16-Bit Timer Output............330 Interrupts ..........................331 9.5.1 Setting of Status Flags ..................331 9.5.2 Timing of Clearing of Status Flags............... 333 9.5.3 Interrupt Sources and DMA Controller Activation ..........334 Usage Notes ........................335 Section 10 8-Bit Timers ......................
Page 15 Section 11 Programmable Timing Pattern Controller (TPC) ........383 11.1 Overview..........................383 11.1.1 Features ......................... 383 11.1.2 Block Diagram...................... 384 11.1.3 Pin Configuration....................385 11.1.4 Register Configuration..................386 11.2 Register Descriptions ......................387 11.2.1 Port A Data Direction Register (PADDR)............387 11.2.2 Port A Data Register (PADR)................
Page 16 12.4 Interrupts ..........................423 12.5 Usage Notes ........................423 Section 13 Serial Communication Interface ..............425 13.1 Overview..........................425 13.1.1 Features ......................... 425 13.1.2 Block Diagram...................... 427 13.1.3 Pin Configuration....................428 13.1.4 Register Configuration..................429 13.2 Register Descriptions ......................430 13.2.1 Receive Shift Register (RSR) ................
Page 17 14.3.5 Clock ........................502 14.3.6 Transmitting and Receiving Data ................. 504 14.4 Usage Notes ........................512 Section 15 A/D Converter ....................515 15.1 Overview..........................515 15.1.1 Features ......................... 515 15.1.2 Block Diagram...................... 516 15.1.3 Pin Configuration....................517 15.1.4 Register Configuration..................518 15.2 Register Descriptions ......................
Page 18 Section 18 Clock Pulse Generator ................... 549 18.1 Overview..........................549 18.1.1 Block Diagram...................... 549 18.2 Oscillator Circuit........................ 550 18.2.1 Connecting a Crystal Resonator................550 18.2.2 External Clock Input ..................... 552 18.3 Duty Adjustment Circuit....................555 18.4 Prescalers ........................... 555 18.5 Frequency Divider......................555 18.5.1 Register Configuration..................
Page 19 20.2.2 AC Characteristics ....................582 20.2.3 A/D Conversion Characteristics ................590 20.2.4 D/A Conversion Characteristics ................592 20.3 Operational Timing......................593 20.3.1 Clock Timing ......................593 20.3.2 Control Signal Timing ..................594 20.3.3 Bus Timing ......................596 20.3.4 DRAM Interface Bus Timing ................602 20.3.5 TPC and I/O Port Timing..................
Page 20 Appendix H Comparison of H8/300H Series Product Specifications ....767 Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3007 and H8/3006, and H8/3002 ................. 767 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) ..770 xiii...
Page 21: Section 1 Overview
Section 1 Overview Overview The H8/3006 and H8/3007 are a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Hitachi architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed.
Page 22 Feature Description Memory H8/3007 • RAM: 4 kbytes H8/3006 • RAM: 2 kbytes • Seven external interrupt pins: NMI, IRQ to IRQ Interrupt • 36 internal interrupts controller • Three selectable interrupt priority levels • Address space can be partitioned into eight areas, with independent bus...
Page 23 Feature Description • Three 16-bit timer channels, capable of processing up to six pulse outputs or 16-bit timer, six pulse inputs 3 channels • 16-bit timer counter (channels 0 to 2) • Two multiplexed output compare/input capture pins (channels 0 to 2) •...
Page 24 2.7 to 5.5 V HD6413007VF 100-pin QFP (FP-100B) (Low HD6413007VTE 100-pin TQFP (TFP-100B) voltage) HD6413007VFP 100-pin QFP (FP-100A) 5 V ± 10% H8/3006 HD6413006F 100-pin QFP (FP-100B) (5 V) HD6413006TE 100-pin TQFP (TFP-100B) HD6413006FP 100-pin QFP (FP-100A) 2.7 to 5.5 V HD6413006VF...
Page 25: Internal Block Diagram
Internal Block Diagram Figure 1-1 shows an internal block diagram. Data bus Port 4 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL STBY H8/300H CPU RESO Interrupt controller DMA controller (DMAC) φ/P6 BACK/P6 BREQ/P6 WAIT/P6 Watchdog timer ADTRG/CS (WDT) /IRQ /IRQ...
Page 26: Pin Description
Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3006, H8/3007 FP-100B and TFP-100B packages is shown in figure 1-2, and that of the FP-100A package in figure 1-3. /IRQ /RFSH Top view /IRQ (FP-100B, TFP-100B) /IRQ /IRQ /ADTRG...
Page 27 /IRQ /RFSH Top view /IRQ (FP-100A) /IRQ /IRQ /ADTRG /TCLKA/TEND /TCLKB/TEND /TIOCA /TCLKC /TIOCB /TCLKD /TIOCA /TIOCB Figure 1-3 Pin Arrangement (FP-100A, Top View)
Page 28: Pin Functions
1.3.2 Pin Functions Table 1-2 summarizes the pin functions. Table 1-2 Pin Functions Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function Power 1, 35, 68 3, 37, 70 Input Power: For connection to the power supply. Connect all V pins to the system power supply.
Page 29 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function System Input Reset input: When driven low, this pin resets control the chip RESO Output Reset output: Outputs the reset signal generated by the watchdog timer to external devices STBY Input Standby: When driven low, this pin forces...
Page 30 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function RFSH DRAM Output Refresh: Indicates a refresh cycle interface Output Row address strobe RAS: Row address 89, 88, 5, 91, 90, 7, 6 strobe signal for DRAM Output Write enable WE: Write enable signal for DRAM Output Upper column address strobe UCAS: UCAS...
Page 31 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function Program- 9 to 2, 11 to 4, Output TPC output 15 to 0: Pulse output mable 100 to 93 2, 1, timing 100 to pattern controller (TPC) Serial 8, 13, 12 10, 15, Output Transmit data (channels 0, 1, 2): SCI data communi-...
Page 32 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function I/O ports to P4 26 to 23, 28 to 25, Input/ Port 4: Eight input/output pins. The direction 21 to 18 23 to 20 output of each pin can be selected in the port 4 data direction register (P4DDR).
Page 33: 1.3.3 Pin Assignments In Each Mode
1.3.3 Pin Assignments in Each Mode Table 1-3 lists the pin assignments in each mode. Table 1-3 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 /TMO /TMO /TMO...
Page 34 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4...
Page 35 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /φ /φ /φ /φ STBY STBY STBY STBY EXTAL EXTAL EXTAL EXTAL XTAL XTAL XTAL XTAL...
Page 36 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 /IRQ /RFSH /IRQ /RFSH /IRQ /RFSH /IRQ /RFSH /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ ADTRG ADTRG ADTRG ADTRG /TCLKA/ /TCLKA/ /TCLKA/ /TCLKA/...
Page 37: Section 2 Cpu
Section 2 CPU Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 38: Differences From H8/300 Cpu
 16 × 16-bit register-register multiply: 1.1 µs  32 ÷ 16-bit register-register divide: 1.1 µs • Two CPU operating modes  Normal mode (not available in the H8/3006 and H8/3007)  Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
Page 39: Cpu Operating Modes
Maximum 64 kbytes, program Normal mode* and data areas combined CPU operating modes Maximum 16 Mbytes, program Advanced mode and data areas combined Note: * Normal mode is not available in the H8/3006 and H8/3007. Figure 2-1 CPU Operating Modes...
Page 40: Address Space
Address Space Figure 2-2 shows a simple memory map for the H8/3006 and H8/3007. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
Page 41: Register Configuration
Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend Stack pointer...
Page 42: General Registers
2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 43: Control Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. Free area SP (ER7) Stack area Figure 2-5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register...
Page 44: Initial Cpu Register Values
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
Page 45: Data Formats
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 46: Memory Data Formats
General Data Type Register Data Format Word data Word data Longword data Legend ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats 2.5.2 Memory Data Formats Figure 2-8 shows the data formats on memory.
Page 47 Data Type Address Data Format 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2-8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
Page 48: Instruction Set
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP. 2. Not available in the H8/3006 and H8/3007. 3. Bcc is a generic branching instruction.
Page 49: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 — Data —...
Page 50: Tables Of Instructions Classified By Function
2.6.3 Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd) Destination operand (EAs)
Page 51 Table 2-3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in this LSI.
Page 52 Table 2-4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 53 Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder Rd ÷...
Page 54 Table 2-5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 55 Table 2-7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 56 Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨...
Page 57 Table 2-8 Branching Instructions Instruction Size Function — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 58 Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 59: 2.6.4 Basic Instruction Formats
Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
Page 60: Notes On Use Of Bit Manipulation Instructions
Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2-9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions...
Page 61 Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Execution of BCLR Instruction ;Clear bit 0 in data direction register BCLR #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output Output Output Output Output Output Input Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR.
Page 62: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
Page 63 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
Page 64: Effective Address Calculation
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
Page 68: Processing States
Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing states.
Page 69: Program Execution State
2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
Page 70 Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2-12 Classification of Exception Sources Bus request End of bus release Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception handling source Bus-released state...
Page 71: Exception-Handling Sequences
2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address.
Page 72: Bus-Released State
2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external bus master.
Page 73: Basic Operational Timing
Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states.
Page 74: On-Chip Supporting Module Access Timing
φ Address bus Address RD HWR LWR High High impedance to D Figure 2-16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the internal I/O register being accessed.
Page 75: Access To External Address Space
φ Address bus Address RD HWR LWR High High impedance to D Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states.
Page 76: Section 3 Mcu Operating Modes
16 Mbytes. The H8/3006 and H8/3007 can be used only in modes 1 to 4. The inputs at the mode pins must select one of these four modes. The inputs at the mode pins must not be changed during operation.
Page 77: Register Configration
3.1.2 Register Configuration The H8/3006 and H8/3007 have a mode control register (MDCR) that indicates the inputs at the mode pins (MD to MD ), and a system control register (SYSCR). Table 3-2 summarizes these registers. Table 3-2 Registers Address*...
Page 78: System Control Register (Syscr)
System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3006 and H8/3007. SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable Enables or disables on-chip RAM Software standby output port enable...
Page 79 Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate.
Page 80 Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS , AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as bus control signals (CS outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE Description...
Page 81: Operating Mode Descriptions
Operating Mode Descriptions 3.4.1 Mode 1 A maximum 1-Mbyte address space can be accessed. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
Page 82: Pin Functions In Each Operating Mode
0 in bits 7 to 5 of BRCR. Memory Map in Each Operating Mode Figure 3-1, 3-2 show a memory maps of the H8/3006 and H8/3007. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
Page 83 Modes 1 and 2 Modes 3 and 4 (1 Mbyte) (16 Mbytes) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'200000 H'3FFFF H'40000 Area 1 Area 2 H'5FFFF H'3FFFFF H'60000 External address Area 3...
Page 84 H'FF8000 space H'FFFFF H'FFF71F H'FFF720 H'FFFF00 On-chip RAM* H'FFFF1F H'FFFF20 Internal I/O registers (2) H'FFFFE9 H'FFFFEA External address space H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3-2 H8/3006 Memory Map in Each Operating Mode...
Page 85: Section 4 Exception Handling
Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 86: Exception Vector Table
4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Page 87 H'0028 to H'0029 H'00FC to H'00FF H'007E to H'007F Notes: 1. Lower 16 bits of the address. 2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table. 3. Normal mode is not available in the H8/3006 and H8/3007.
Page 88: Reset
Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high.
Page 89 Figure 4-2 Reset Sequence (Modes 1 and 3)
Page 90: Interrupts After Reset
Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 91: Interrupts
Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ), and 36 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication interface (SCI), and A/D converter.
Page 92: Stack Status After Exception Handling
Figure 4-5 Stack after Completion of Exception Handling Notes on Stack Usage When accessing word data or longword data, the H8/3006 and H8/3007 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP: ER7) should always be kept even.
Page 93 Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what happens when the SP value is odd. H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP CCR contents lost Legend...
Page 94: Section 5 Interrupt Controller
Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
Page 95: Block Diagram
5.1.2 Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number TEIE Interrupt controller SYSCR Legend ISCR: IRQ sense control register IER: IRQ enable register ISR:...
Page 96: Pin Configuration
5.1.3 Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Abbreviation I/O Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable to IRQ External interrupt request 5 to 0 Input Maskable interrupts, falling edge or level sensing selectable 5.1.4 Register Configuration...
Page 97: Register Descriptions
Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR).
Page 98: Interrupt Priority Registers A And B (Ipra, Iprb)
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 99 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests...
Page 100 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 101 Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests. Bit 3 IPRA3 Description WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low priority) (Initial value) WDT, DRAM interface, and A/D converter interrupt requests have priority level 1 (high priority) Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests.
Page 102 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 IPRB5 — IPRB3 IPRB2 IPRB1 — Initial value Read/Write Reserved bit Priority level B1 Selects the priority level of SCI channel 2 interrupt requests Priority level B2 Selects the priority level of...
Page 103 Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 Description 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests.
Page 104 Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 Description SCI0 interrupt requests have priority level 0 (low priority) (Initial value) SCI0 interrupt requests have priority level 1 (high priority) Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 Description...
Page 105: Irq Status Register (Isr)
5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ to IRQ interrupt requests. — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) *...
Page 106: Irq Enable Register (Ier)
5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ to IRQ interrupt requests. — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write IRQ to IRQ enable Reserved bits These bits enable or disable IRQ to IRQ interrupts IER is initialized to H'00 by a reset and in hardware standby mode.
Page 107: Irq Sense Control Register (Iscr)
5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ — — IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write IRQ to IRQ sense control Reserved bits These bits select level sensing or falling-edge sensing for IRQ to IRQ interrupts...
Page 108: Interrupt Sources
Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 36 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR.
Page 109: Internal Interrupts
Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Page 110 Table 5-3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Interrupt Source Origin Vector Number Advanced Mode Priority External H'001C to H'001F — High pins H'0030 to H'0033 IPRA7 H'0034 to H0037 IPRA6 H'0038 to H'003B IPRA5 H'003C to H'003F H'0040 to H'0043 IPRA4 H'0044 to H'0047...
Page 111 Vector Address* Interrupt Source Origin Vector Number Advanced Mode Priority IMIA2 16-bit timer H'0080 to H'0083 IPRA0 High (compare match/ channel 2 input capture A2) IMIB2 H'0084 to H'0087 (compare match/ input capture B2) OVI2 (overflow 2) H'0088 to H'008B Reserved —...
Page 112 Vector Address* Interrupt Source Origin Vector Number Advanced Mode Priority ERI0 H'00D0 to H'00D3 IPRB3 High (receive error 0) channel 0 RXI0 (receive H'00D4 to H'00D7 data full 0) H'00D8 to H'00DB TXI0 (transmit data empty 0) TEI0 H'00DC to H'00DF (transmit end 0) ERI1 H'00E0 to H'00E3...
Page 113: Interrupt Operation
5.4.1 Interrupt Handling Process The H8/3006 and H8/3007 handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5-4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits.
Page 114 Program execution state Interrupt requested? Pending Priority level 1? TEI2 TEI2 I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when UE = 1 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Page 115 priority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5-3. • The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted.
Page 116 Figure 5-5 shows the transitions among the above states. ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5-5 Interrupt Masking State Transitions (Example)
Page 117 Program execution state Interrupt requested? Pending Priority level 1? TEI2 TEI2 I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5-6 Process Up to Interrupt Acceptance when UE = 0...
Page 118: Interrupt Sequence
5.4.2 Interrupt Sequence Figure 5-7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5-7 Interrupt Sequence...
Page 119: Interrupt Response Time
5.4.3 Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip Item Memory...
Page 120: Usage Notes
Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 121: Instructions That Inhibit Interrupts
5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 122: Section 6 Bus Controller
Section 6 Bus Controller Overview The H8/3006 and H8/3007 have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 123 • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle •...
Page 124: Block Diagram
6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. to CS ABWCR ASTCR Area Internal address bus CSCR Internal signals decoder Chip select Bus mode control signal control signals Bus control Bus size control signal circuit Access state control signal Wait request signal Wait state...
Page 125: Pin Configuration
6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus Read Output...
Page 126: Register Configuration
6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address* Name Abbreviation Initial Value H'EE020 Bus width control register ABWCR H'FF* H'EE021 Access state control register ASTCR H'FF H'EE022 Wait control register H WCRH H'FF H'EE023 Wait control register L...
Page 127: Register Descriptions
Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Initial value Modes 1 and 3 Read/Write Modes Initial value 2 and 4 Read/Write When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus...
Page 128: Access State Control Register (Astcr)
6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode.
Page 129 WCRH Initial value Read/Write Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
Page 130 Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of...
Page 131 Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 Bit 4 Description Program wait not inserted when external space area 2 is accessed...
Page 132: Bus Release Control Register (Brcr)
6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. A23E A22E A21E A20E — — — BRLE Initial value Modes...
Page 133: Bus Control Register (Bcr)
Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A output from PA . In modes 1 and 2, this bit cannot be modified and PA has its ordinary port functions. Bit 5 A21E Description...
Page 134 Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 Description No idle cycle inserted in case of consecutive external read cycles for different areas Idle cycle inserted in case of consecutive external read cycles for different areas...
Page 135: Chip Select Control Register (Cscr)
Bit 3 BRSTS0 Description Max. 4 words in burst access (burst access on match of address bits above A3) (Initial value) Max. 8 words in burst access (burst access on match of address bits above A4) Bit 2—Reserved: Read-only bit, always read as 1. Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units.
Page 136: Dram Control Register A (Drcra)
CS7E CS6E CS5E CS4E — — — — Initial value Read/Write — — — — Chip select 7 to 4 enable Reserved bits These bits enable or disable chip select signal output CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 137 Description Bit 7 Bit 6 Bit 5 DRAS2 DRAS1 DRAS0 Area 5 Area 4 Area 3 Area 2 Normal Normal Normal Normal Normal Normal Normal DRAM space Normal Normal DRAM space DRAM space Normal Normal DRAM space (CS Normal DRAM space DRAM space DRAM space DRAM space...
Page 138: Dram Control Register B (Drcrb)
Bit 2 Description DRAM interface: RAS up mode selected (Initial value) DRAM interface: RAS down mode selected Bit 1—Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby mode. When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a transition is made to software standby mode after the SRFMD bit has been set to 1.
Page 139 DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0. Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface.
Page 140 Bit 4—Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit. Bit 4 RCYCE Description Refresh cycles disabled (Initial value)
Page 141: Refresh Timer Control/Status Register (Rtmcsr)
6.2.9 Refresh Timer Control/Status Register (RTMCSR) CMIE CKS2 CKS1 CKS0 — — — Initial value Read/Write R(W)* — — — RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests. Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes.
Page 142: Refresh Timer Counter (Rtcnt)
Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Description Count operation halted (Initial value) φ/2 used as counter clock φ/8 used as counter clock φ/32 used as counter clock φ/128 used as counter clock φ/512 used as counter clock φ/2048 used as counter clock φ/4096 used as counter clock Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 1.
Page 143: Refresh Time Constant Register (Rtcor)
6.2.11 Refresh Time Constant Register (RTCOR) Initial value Read/Write RTCOR is an 8-bit readable/writable register that sets the RTCNT compare-match interval. RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1 in RTMCSR, and RTCNT is simultaneously cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode.
Page 144: Operation
Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
Page 145 H'000000 Area 0 Area 0 2 Mbytes 2 Mbytes H'1FFFFF H'200000 Area 1 Area 1 2 Mbytes 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes Area 2 H'5FFFFF 8 Mbytes H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5...
Page 146: Bus Specifications
6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller.
Page 147: Memory Interfaces
Chip Select Signals to CS For each of areas 0 to 7, the H8/3006 and H8/3007 can output a chip select signal (CS ) that goes low when the corresponding area is selected. Figure 6.4 shows the output timing of a CSn signal.
Page 148 Output of CS to CS : Output of CS to CS is enabled or disabled in the chip select control register (CSCR). A reset leaves pins CS to CS in the input state. To output chip select signals to CS , the corresponding CSCR bits must be set to 1.
Page 149: Basic Bus Interface
Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D...
Page 150: Valid Strobes
In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
Page 151: Memory Areas
Table 6.4 Data Buses Used and Valid Strobes Area Access Read/Write Address Valid Strobe Upper Data Bus Lower Data Bus Size to D to D 8-bit Byte Read — Valid Invalid access area Write — Undetermined data 16-bit Byte Read Even Valid Invalid...
Page 152 Area 7: Area 7 includes the on-chip RAM and registers. The space excluding the on-chip RAM and registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space .
Page 153: Basic Bus Control Signal Timing
6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.7 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states data bus (D to D can be inserted.
Page 154 8-Bit, Two-State-Access Areas Figure 6.8 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states data bus (D to D cannot be inserted.
Page 155 16-Bit, Three-State-Access Areas Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 156 Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.10 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address)
Page 157 Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D to D Valid Note: n = 7 to 0 Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access)
Page 158 16-Bit, Two-State-Access Areas: Figures 6.12 to 6.14 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 159 Bus cycle φ Address bus Odd external address in area n to D Read access Invalid to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address)
Page 160: Wait Control
(Word Access) 6.4.6 Wait Control When accessing external space, the H8/3006 and H8/3007 can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin.
Page 161 This is useful when inserting four or more T states, or when changing the number of T states for different external devices. The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space. Figure 6.15 shows an example of the timing for insertion of one program wait state in 3-state space.
Page 162: Dram Interface
6.5.1 Overview The H8/3006 and H8/3007 are provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM space accessed via the DRAM interface.
Page 163: Address Multiplexing
6.5.3 Address Multiplexing When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of MXC1 and MXC0 and the address multiplexing method.
Page 164: Basic Timing
Table 6.7 DRAM Interface Pins With DRAM Designated Name Function UCAS Upper column Output Upper column address strobe for DRAM address strobe space access (when CSEL = 0 in DRCRB) LCAS Lower column Output Lower column address strobe for DRAM address strobe space access (when CSEL = 0 in DRCRB) UCAS...
Page 165: Precharge State Control
Figure 6.16 Basic Access Timing (CSEL = 0 in DRCRB) 6.5.7 Precharge State Control In the H8/3006 and H8/3007, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (T ) when DRAM space is accessed. This can be changed to two T states by setting the TPC bit to 1 in DRCRB.
Page 166: Wait Control
φ Column to A High CSn (RAS) PB4 /PB5 (UCAS /LCAS) Read access RD(WE) High to D PB4 /PB5 (UCAS /LCAS) Write access RD(WE) 15 to Note: n = 2 to 5 Figure 6.17 Timing with Two Precharge States (CSEL = 0 in DRCRB) 6.5.8 Wait Control In a DRAM access cycle, wait states can be inserted (1) between the T...
Page 167: Byte Access Control And Cas Output Pin
The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin. φ Column to A High CSn(RAS) PB4 /PB5...
Page 168 When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output port. Note that RAS down mode cannot be used when a device other than DRAM is connected to external space and HWR and LWR are used as write strobes.
Page 169: Burst Operation
6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output.
Page 170 Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB ABWCR Operating Mode MXC1 MXC0 ABWn Bus Width Compared Row Address Modes 1 and 2 16 bits A19 to A9 (1-Mbyte) 8 bits A19 to A8...
Page 171 External space access DRAM access DRAM access φ to A CSn (RAS) PB4/PB5 (UCAS/LCAS) to D Note: n = 2 to 5 Figure 6.21 Example of Operation Timing in RAS Down Mode (CSEL = 0) When RAS down mode is selected, the conditions for an asserted RASn signal to return to the high level are as shown below.
Page 172 DRAM access cycle φ RASn (a) Access to DRAM space with a different row address CBR refresh cycle φ RASn (b) CAS-before-RAS refresh cycle DRCRA write cycle φ RASn (c) BE bit or RDM bit cleared to 0 in DRCRA External bus released φ...
Page 173 When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval setting must be made so that the maximum DRAM RAS pulse width specification is observed.
Page 174: Refresh Control
6.5.11 Refresh Control The H8/3006 and H8/3007 are provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in DRCRB. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR (compare match).
Page 175 φ RTCNT H'00 RTCOR Refresh request signal and CMF bit setting signal Figure 6.25 Compare Match Timing φ Area 2 start address Address bus (RAS) PB4/PB5 (UCAS/LCAS) RD(WE) High RFSH High Figure 6.26 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0) The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T ) state, and two RAS output cycle (T...
Page 176 Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. The H8/3006 and H8/3007 have a function that places the DRAM in self-refresh mode when the chip enters software standby mode.
Page 177: Examples Of Use
The following conditions must be observed when the self-refresh function is used: • When burst access is selected, RAS up mode must be selected before executing a SLEEP instruction in order to enter software standby mode. Therefore, if RAS down mode has been selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before executing the SLEEP instruction.
Page 178 10-bit row address × 10-bit column address type. Up to four DRAMs can be connected by designating areas 2 to 5 as DRAM space. 2-CAS 16-Mbit DRAM 10-bit row address x 10-bit column address x16-bit organization H8/3006 and H8/3007 CS2 (RAS2) CS3 (RAS3) UCAS PB4 (UCAS)
Page 179 DRAM with address space that spans a maximum of four areas. Any unused CS pins (in this example, the CS3 pin) can be used as input/output ports. 2-CAS 16-Mbit DRAM 11-bit row address x 10-bit column address H8/3006 and H8/3007 x8-bit organization CS2 (RAS2) PB4 (UCAS)
Page 180 The RFSH pin is used in this case, since both DRAMs must be refreshed simultaneously. However, note that RAS down mode cannot be used in this interconnection example. 2-CAS 4-Mbit DRAM 9-bit row address x 9-bit column address H8/3006 and H8/3007 x16-bit organization CS2 (RAS2) UCAS PB4 (UCAS)
Page 181: Usage Notes
Example of Program Setup Procedure: Figure 6.32 shows an example of the program setup procedure. Set ABWCR Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Set DRCRB Set DRCRA Wait for DRAM stabilization time DRAM can be accessed Figure 6.32 Example of Setup Procedure when Using DRAM Interface 6.5.13 Usage Notes Note the following points when using the DRAM refresh function.
Page 182 When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction. Similar contention in a transition to self-refresh mode may prevent dependable strobe waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR. •...
Page 183 Oscillation stabilization CPU internal cycle CPU cycle time on exit from software (period in which external standby mode bus can be released) φ Address Figure 6.35 Self-Refresh Clearing...
Page 184: Interval Timer
6.6.1 Operation When DRAM is not connected to the H8/3006 and H8/3007 chip, the refresh timer can be used as an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
Page 185 φ RTCNT address Address bus Internal write signal Counter clear signal RTCNT H'00 Figure 6.37 Contention between RTCNT Write and Clear Contention between RTCNT Write and Increment: If an increment pulse occurs in the T state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See Figure 6.38. φ...
Page 186 Contention between RTCOR Write and Compare Match: If a compare match occurs in the T state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See Figure 6.39. φ Address bus RTCOR address Internal write signal RTCNT RTCOR RTCOR write data...
Page 187 Table 6.10 Internal Clock Switchover and RTCNT Operation CKS2 to CKS0 RTCNT Operation Write Timing switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten High switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten...
Page 188 CKS2 to CKS0 RTCNT Operation Write Timing High switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten High High switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted state to a low clock source.
Page 189: Interrupt Sources
6.8.1 Overview With the H8/3006 and H8/3007, external space area 0 can be designated as burst ROM space, and burst ROM space interfacing can be performed. The burst ROM interface enables ROM with burst access capability to be accessed at high speed. Area 0 is designated as burst ROM space by means of the BROME bit in BCR.
Page 190: Wait Control
Full access Burst access φ Address bus Only lower address changes Data bus Read data Read data Read data Figure 6.40 Example of Burst ROM Access Timing 6.8.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface.
Page 191: Idle Cycle
6.9.1 Operation When the H8/3006 and H8/3007 chip accesses external space, it can insert a 1-state idle cycle (T between bus cycles in the following cases: (1) when read accesses between different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when external address space other than DRAM space is accessed immediately after a DRAM space access.
Page 192: Operation
Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ φ Address bus Address bus Data bus Data bus Data collision Long buffer-off time (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.42 Example of Idle Cycle Operation (2) (ICIS0 = 1) External Address Space Access Immediately after DRAM Space Access: If a DRAM space access is followed by a non-DRAM external access when HWR and LWR have been selected as the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted...
Page 193 Bus cycle A Bus cycle A (DRAM access cycle) Bus cycle B (DRAM access cycle) Bus cycle B φ φ Address bus Address bus HWR/LWR HWR/LWR (UCAS/LCAS) (UCAS/LCAS) Simultaneous change of HWR/LWR and CSn (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS) External read DRAM space read...
Page 194: Pin States In Idle Cycle
Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ φ Address bus Address bus Simultaneous change of RD and CSn Possibility of mutual overlap (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.45 Example of Idle Cycle Operation (5) 6.9.2 Pin States in Idle Cycle Table 6.11 shows the pin states in an idle cycle.
Page 195: Bus Arbiter
6.10 Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right.
Page 196 BREQ signal goes high. While the bus is released to an external bus master, the H8/3006 and H8/3007 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK pin in the low output state.
Page 197 CPU cycles External bus released CPU cycles φ High-impedance Address Address bus High-impedance Data bus High-impedance High-impedance High High-impedance HWR, LWR BREQ BACK Minimum 3 cycles Figure 6.46 Example of External Bus Master Operation In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.34).
Page 198: Register And Pin Input Timing
6.11 Register and Pin Input Timing 6.11.1 Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.47 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. φ...
Page 199: Breq Pin Input Timing
BRCR Write Timing: Data written to BRCR to switch between A , or A output and generic input or output takes effect starting from the T state of the BRCR write cycle. Figure 6.49 shows the timing when a pin is changed from generic input to A , or A output.
Page 200: Section 7 Dma Controller
Section 7 DMA Controller Overview The H8/3006 and H8/3007 have an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 19.6, Module Standby Function.
Page 201: Block Diagram
7.1.2 Block Diagram Figure 7.1 shows a DMAC block diagram. Internal address bus Address buffer Internal IMIA0 interrupts IMIA1 Arithmetic-logic unit IMIA2 TXI0 MAR0A RXI0 Channel IOAR0A ETCR0A Channel DREQ Control logic DREQ MAR0B TEND Channel IOAR0B TEND DTCR0A ETCR0B Interrupt DEND0A DTCR0B...
Page 202: Functional Overview
7.1.3 Functional Overview Table 7.1 gives an overview of the DMAC functions. Table 7.1 DMAC Functional Overview Address Reg. Length Destina- Transfer Mode Activation Source tion • Compare match/input Short I/O mode capture A interrupts from 16- address • Transfers one byte or one word bit timer channels mode per request...
Page 203: Pin Configuration
7.1.4 Pin Configuration Table 7.2 lists the DMAC pins. Table 7.2 DMAC Pins Abbrevia- Input/ Channel Name tion Output Function DREQ DMA request 0 Input External request for DMAC channel 0 TEND Transfer end 0 Output Transfer end on DMAC channel 0 DREQ DMA request 1 Input...
Page 204 Table 7.3 DMAC Registers Channel Address* Name Abbreviation R/W Initial Value H'FFF20 Memory address register 0AR MAR0AR Undetermined H'FFF21 Memory address register 0AE MAR0AE Undetermined H'FFF22 Memory address register 0AH MAR0AH Undetermined H'FFF23 Memory address register 0AL MAR0AL Undetermined H'FFF26 I/O address register 0A IOAR0A Undetermined...
Page 205: Register Descriptions (1) (Short Address Mode)
Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 7.4. Table 7.4 Selection of Short and Full Address Modes Bit 2...
Page 206: I/O Address Registers (Ioar)
7.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF). Initial value Undetermined Read/Write...
Page 207 • Repeat mode Initial value Undetermined Read/Write ETCRH Transfer counter Initial value Undetermined Read/Write ETCRL Initial count In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
Page 208: Data Transfer Control Registers (Dtcr)
7.2.4 Data Transfer Control Registers (DTCR) A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel. DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer enable Data transfer select Enables or disables These bits select the data data transfer...
Page 209 Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode. Bit 5 DTID Description...
Page 210 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source.
Page 211: Register Descriptions (2) (Full Address Mode)
Register Descriptions (2) (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 7.4. 7.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register.
Page 212: Execute Transfer Count Registers (Etcr)
7.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. • Normal mode ETCRA Initial value Undetermined...
Page 213 • Block transfer mode ETCRA Initial value Undetermined Read/Write ETCRAH Block size counter Initial value Undetermined Read/Write ETCRAL Initial block size ETCRB Initial value Undetermined Read/Write Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size.
Page 214: Data Transfer Control Registers (Dtcr)
7.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode.
Page 215 Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested.
Page 216 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1.
Page 217 DTCRB DTME — DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Data transfer master enable Enables or disables data transfer, together with Transfer mode select the DTE bit, and is cleared Selects whether the to 0 by an interrupt block area is the source or destination in block Reserved bit transfer mode...
Page 218 Bit 6—Reserved: Although reserved, this bit can be written and read. Bit 5—Destination Address Increment/Decrement (DAID) and, Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer.
Page 219 Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B...
Page 220: Operation
Operation 7.4.1 Overview Table 7.5 summarizes the DMAC modes. Table 7.5 DMAC Modes Transfer Mode Activation Notes • Short address I/O mode Compare match/input Up to four channels mode Idle mode capture A interrupt from can operate Repeat mode 16-bit timer channels 0 to 2 independently •...
Page 221 Repeat Mode: One byte or word is transferred per request. A designated number of these transfers are executed. When the designated number of transfers are completed, the initial address and counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit address and one 8-bit address are specified.
Page 222: I/O Mode
7.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR).
Page 223 Figure 7.2 illustrates how I/O mode operates. Address T Transfer IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCR Address T = L DTID DTSZ Address B = L + (–1) •...
Page 224: Idle Mode
Figure 7.3 shows a sample setup procedure for I/O mode. I/O mode setup Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. Set source and Set the transfer count in ETCR. destination addresses Read DTCR while the DTE bit is cleared to 0.
Page 225 Table 7.7 Register Functions in Idle Mode Function Activated by SCI0 Receive- Data-Full Interrupt or A/D Converter Conversion Other Register End Interrupt Activation Initial Setting Operation Destination Source Destination or Held fixed address address source address register register Source Destination Source or Held fixed address...
Page 226 The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000.
Page 227: Repeat Mode
7.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode.
Page 228 Table 7.8 Register Functions in Repeat Mode Function Activated by SCI0 Receive- Data-Full Interrupt or A/D Converter Conversion Other End Interrupt Register Activation Initial Setting Operation Destination Source Transfer Incremented or address address destination or decremented at register register transfer source each transfer until start address ETCRH reaches...
Page 229 As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 7.6 illustrates how repeat mode operates.
Page 230 Repeat mode Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. Set the transfer count in both ETCRH and ETCRL. Set source and Read DTCR while the DTE bit is cleared to 0. destination addresses Set the DTCR bits as follows.
Page 231: Normal Mode
7.4.5 Normal Mode In normal mode, the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 7.9 indicates the register functions in I/O mode. Table 7.9 Register Functions in Normal Mode Register...
Page 232 Figure 7.8 illustrates how normal mode operates. Address T Transfer Address T Address B Address B Legend = initial setting of MARA = initial setting of MARB = initial setting of ETCRA SAID DTSZ = L + SAIDE • (–1) •...
Page 233 Figure 7.9 shows a sample setup procedure for normal mode. Normal mode Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA. Set the DTCRB bits as follows. Set initial source address •...
Page 234 7.4.6 Block Transfer Mode In block transfer mode, the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 7.10 indicates the register functions in block transfer mode.
Page 235 If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N. Figure 7.10 illustrates how block transfer mode operates.
Page 236 When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented.
Page 237 Start Start (DTE = DTME = 1) (DTE = DTME = 1) Transfer requested? Transfer requested? Get bus Get bus Read from MARA address Read from MARA address MARA = MARA + 1 MARA = MARA + 1 Write to MARB address Write to MARB address MARB = MARB + 1 ETCRAH = ETCRAH –...
Page 238: Block Transfer Mode
Figure 7.12 shows a sample setup procedure for block transfer mode. Block transfer mode Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) Set source address in both ETCRAH and ETCRAL.
Page 239: Dmac Activation
7.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 7.11. Table 7.11 DMAC Activation Sources Short Address Mode Channels Channels Full Address Mode...
Page 240 Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be level- sensitive or edge-sensitive.
Page 241: Dmac Bus Cycle
7.4.8 DMAC Bus Cycle Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (T ), it reads from the source address and writes to the destination address.
Page 242 Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. DMAC cycle CPU cycle DMAC cycle...
Page 243 Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. CPU cycle DMAC cycle CPU cycle φ Source Destination address address Address Figure 7.15 Burst DMA Bus Timing When the DMAC is activated from a DREQ pin there is a minimum interval of four states from when the transfer is requested until the DMAC starts operating*.
Page 244 Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. CPU cycle DMAC cycle cycle DMAC cycle φ DREQ Address Minimum 4 states Next sampling point Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode...
Page 245 Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. CPU cycle DMAC cycle CPU cycle φ DREQ Address Minimum 4 states Next sampling point Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode...
Page 246 Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. End of 1 block transfer DMAC cycle CPU cycle DMAC cycle φ DREQ Address TEND Next sampling Minimum 4 states Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode...
Page 247: Multiple-Channel Operation
7.4.9 Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 7.12 shows the complete priority order. Table 7.12 Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B...
Page 248: External Bus Requests, Dram Interface, And Dmac
DMAC cycle DMAC cycle DMAC cycle (channel 1) cycle (channel 0A) cycle (channel 1) φ Address Figure 7.19 Timing of Multiple-Channel Operations 7.4.10 External Bus Requests, DRAM Interface, and DMAC During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer of the current byte or word.
Page 249: Nmi Interrupts And Dmac
7.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0.
Page 250: Aborting A Dmac Transfer
7.4.12 Aborting a DMAC Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose.
Page 251: Exiting Full Address Mode
7.4.13 Exiting Full Address Mode Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode. Exiting full address mode Clear the DTE bit to 0 in DTCRA, or wait for the transfer to end and the DTE bit...
Page 252: Dmac States In Reset State, Standby Modes, And Sleep Mode
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters hardware standby mode or software standby mode, the DMAC is initialized and halts.DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer in sleep mode.
Page 253: Interrupts
Interrupts The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority. Table 7.13 DMAC Interrupts Description Interrupt Short Address Mode Full Address Mode Interrupt Priority DEND0A End of transfer on channel 0A End of transfer on channel 0 High DEND0B End of transfer on channel 0B...
Page 254: Usage Notes
Usage Notes 7.6.1 Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 7.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified as source or destination addresses.
Page 255: Note On Activating Dmac By Internal Interrupts
7.6.5 Note on Activating DMAC by Internal Interrupts When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled.
Page 256: Nmi Interrupts And Block Transfer Mode
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests.
Page 257: Bus Cycle When Transfer Is Aborted
Table 7.14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode 16-Mbyte Mode H'00000 to H'FFFFF H'000000 to H'FFFFFF (0 to 1048575) (0 to 16777215) IOAR H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1048320 to 1048575) (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode. 7.6.8 Bus Cycle when Transfer is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME...
Page 258: Section 8 I/O Ports
Section 8 I/O Ports Overview The H8/3006 and H8/3007 have 6 input/output ports (ports 4, 6, 8, 9, A, and B) and one input-only port (port 7). Table 8.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 8.1.
Page 259 Table 8.1 Port Functions Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 • 8-bit I/O port Port 4 to P4 Data input/output (D to D ) and 8-bit generic input/ to D output • Built-in input 8-bit bus mode: generic input/output16-bit bus pull-up mode: data input/output transistors...
Page 260 Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 • 8-bit I/O port Port A /TIOCB Output (TP ) from pro- Address output (A grammable timing • Schmitt inputs pattern controller (TPC), input or output (TIOCB for 16-bit timer and generic input/output /TIOCA TPC output (TP...
Page 261: Overview
Port 4 8.2.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.1. When the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus.
Page 262 8.2.2 Register Configuration Table 8.2 summarizes the registers of port 4. Table 8.2 Port 4 Registers Address* Name Abbreviation Initial Value H'EE003 Port 4 data direction register P4DDR H'00 H'FFFD3 Port 4 data register P4DR H'00 H'EE03E Port 4 input pull-up control register P4PCR H'00 Note:...
Page 263 Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4. When port 4 functions as an output port, the value of this register is output. When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin level is read.
Page 264 Table 8.3 Input Pull-Up Transistor States (Port 4) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 8-bit bus mode On/off On/off 16-bit bus mode Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off. Port 6 8.3.1 Overview...
Page 265 8.3.2 Register Configuration Table 8.4 summarizes the registers of port 6. Table 8.4 Port 6 Registers Address* Name Abbreviation Initial Value H'EE005 Port 6 data direction register P6DDR H'80 H'FFFD5 Port 6 data register P6DR H'80 Note: * Lower 20 bits of the address in advanced mode. Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6.
Page 266 Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data for port 6. When port 6 functions as an output port, the value of this register is output. Initial value Read/Write Data for port 6 pins Bits storing data for port 1 pins Reserved bit Note: * Determined by pin P6...
Page 267 Table 8.5 Port 6 Pin Functions Pin Functions and Selection Method /φ Bit PSTOP in MSTCRH selects the pin function as follows. PSTOP φ output Pin function input /BACK Bit BRLE in BRCR and bit P6 DDR select the pin function as follows. BRLE —...
Page 268 Port 7 8.4.1 Overview Port 7 is an 8-bit input-only port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.3 shows the pin configuration of port 7.
Page 269: Port 7
8.4.2 Register Configuration Table 8.6 summarizes the port 7 register. Port 7 is an input-only port, and so has no data direction register. Table 8.6 Port 7 Data Register Address* Name Abbreviation Initial Value H'FFFD6 Port 7 data register P7DR Undetermined Note: Lower 20 bits of the address in advanced mode.
Page 270: Overview
Port 8 8.5.1 Overview Port 8 is a 5-bit input/output port that is also used for CS to CS output, RFSH output, IRQ input, and A/D converter ADTRG input. Figure 8.4 shows the pin configuration of port 8. See table 8.8 for the selection of pin functions. See section 15, A/D Converter, for a description of the A/D converter's ADTRG input pin.
Page 271: Register Configuration
8.5.2 Register Configuration Table 8.7 summarizes the registers of port 8. Table 8.7 Port 8 Registers Initial Value Address* Name Abbreviation Mode 1 to 4 H'EE007 Port 8 data direction P8DDR H'F0 register H'FFFD7 Port 8 data register P8DR H'E0 Note: Lower 20 bits of the address in advanced mode.
Page 272 P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore, when port 8 functions as an input/output port, if a transition is made to software standby mode while a P8DDR bit is set to 1, the corresponding pin maintains its output state.
Page 273 Table 8.8 Port 8 Pin Functions Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows. Pin function input output /IRQ /ADTRG Bit P8 DDR selects the pin function as follows Pin function input output input ADTRG input /IRQ The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P8...
Page 274 Port 9 8.6.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Page 275: Port 9
8.6.2 Register Configuration Table 8.9 summarizes the registers of port 9. Table 8.9 Port 9 Registers Address* Name Abbreviation Initial Value H'EE008 Port 9 data direction register P9DDR H'C0 H'FFFD8 Port 9 data register P9DR H'C0 Note: Lower 20 bits of the address in advanced mode. Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9.
Page 276 Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read.
Page 277 Table 8.10 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P9 DDR select the pin function as follows. CKE1 — CKE0 — — —...
Page 278: Port A
Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows. SMIF — — — Pin function input output output output* Note: * Functions as the TxD output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance.
Page 279 Port A pins PA /TP /TIOCB /A PA /TP /TIOCA /A PA /TP /TIOCB /A PA /TP /TIOCA /A Port A PA /TP /TIOCB /TCLKD PA /TP /TIOCA /TCLKC PA /TP /TEND /TCLKB PA /TP /TEND /TCLKA Pin functions in modes 1 and 2 PA (input/output)/TP (output)/TIOCB (input/output) PA (input/output)/TP (output)/TIOCA (input/output) PA (input/output)/TP (output)/TIOCB (input/output)
Page 280: Register Configuration
8.7.2 Register Configuration Table 8.11 summarizes the registers of port A. Table 8.11 Port A Registers Initial Value Address* Name Abbreviation Modes 1, 2 Modes 3, 4 H'EE009 Port A data direction PADDR H'00 H'80 register H'FFFD9 Port A data register PADR H'00 H'00...
Page 281 Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Page 282 Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit PA DDR select the pin TIOCA function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below —...
Page 283 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit PA DDR select the pin TIOCA function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below —...
Page 284 Table 8.13 Port A Pin Functions (Modes 3, 4) Pin Functions and Selection Method Always used as A output. TIOCB Pin function output Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in BRCR, and bit PA TIOCA select the pin function as follows.
Page 285 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in BRCR, and bit PA TIOCA select the pin function as follows. A23E 16-bit timer channel 1 settings (1) in table below (2) in table below —...
Page 286 Table 8.14 Port A Pin Functions (Modes 1 to 4) Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, TIOCB bits CKS2 to CKS0 in TCR3 of the 8-bit timer, bit NDER3 in NDERA, and bit PA DDR select the pin function TCLKD as follows.
Page 287 Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, TIOCA bits CKS2 to CKS0 in TCR1 of the 8-bit timer, bit NDER2 in NDERA, and bit PA DDR select the pin function TCLKC as follows.
Page 288 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, bits CKS2 to CKS0 in TCR2 of TCLKB/ the 8-bit timer, bit NDER1 in NDERA, and bit PA DDR select the pin function as follows. TEND NDER1 —...
Page 289: Port B
Port B 8.8.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TMIO , TMO , TMIO , TMO ) by the 8-bit timer, CS to CS , DREQ output, input (DREQ...
Page 290: Register Configuration
8.8.2 Register Configuration Table 8.15 summarizes the registers of port B. Table 8.15 Port B Registers Address* Name Abbreviation Initial Value H'EE00A Port B data direction register PBDDR H'00 H'FFFDA Port B data register PBDR H'00 Note: Lower 20 bits of the address in advanced mode. Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B.
Page 291 Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read.
Page 292 Table 8.16 Port B Pin Functions Pin Functions and Selection Method Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB DDR select the pin function as follows. SMIF — — — NDER15 —...
Page 293 Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in TCSR3, bits TMIO CCLR1 and CCLR0 in TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB DDR select the pin DREQ function as follows.
Page 294 Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in TCSR1, bits CCLR1 and CCLR0 in TCR1, bit CS6E in CSCR, bit NDER9 in TMIO NDERB, and bit PB DDR select the pin function as follows. DREQ OIS3/2 and OS1/0 All 0 Not all 0 CS6E...
Page 295: Section 9 16-Bit Timer
Section 9 16-Bit Timer Overview The H8/3006 and H8/3007 have built-in 16-bit timer module with three 16-bit counter channels. 9.1.1 Features 16-bit timer features are listed below. • Capability to process up to 6 pulse outputs or 6 pulse inputs •...
Page 296 • Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. • High-speed access via internal 16-bit bus The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus. • Any initial timer output value can be set •...
Page 297 Table 9.1 16-bit timer Functions Item Channel 0 Channel 1 Channel 2 Internal clocks: φ, φ/2, φ/4, φ/8 Clock sources External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers (output GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 compare/input capture registers) Input/output pins TIOCA , TIOCB...
Page 298: Block Diagrams
9.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer. IMIA0 to IMIA2 TCLKA to TCLKD Clock selector IMIB0 to IMIB2 φ, φ/2, φ/4, φ/8 OVI0 to OVI2 Control logic TIOCA to TIOCA TIOCB to TIOCB TSTR...
Page 299 Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 9.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 IMIB0 Comparator OVI0 Module data bus Legend...
Page 300 Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2 TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2 IMIB2 Comparator OVI2 Module data bus Legend 16TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) ×...
Page 301: Pin Configuration
9.1.3 Pin Configuration Table 9.2 summarizes the 16-bit timer pins. Table 9.2 16-bit timer Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input...
Page 302: Register Configuration
9.1.4 Register Configuration Table 9.3 summarizes the 16-bit timer registers. Table 9.3 16-bit timer Registers Abbre- Initial Channel Address* Name viation Value Common H'FFF60 Timer start register TSTR H'F8 H'FFF61 Timer synchro register TSNC H'F8 H'FFF62 Timer mode register TMDR H'98 H'FFF63 Timer output level setting register...
Page 303 Abbre- Initial Channel Address* Name viation Value H'FFF78 Timer control register 2 16TCR2 H'80 H'FFF79 Timer I/O control register 2 TIOR2 H'88 H'FFF7A Timer counter 2H 16TCNT2H R/W H'00 H'FFF7B Timer counter 2L 16TCNT2L R/W H'00 H'FFF7C General register A2H GRA2H H'FF H'FFF7D...
Page 304: Register Descriptions
Register Descriptions 9.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in channels 0 to 2. — — — — — STR2 STR1 STR0 Initial value Read/Write — — — —...
Page 305: Timer Synchro Register (Tsnc)
9.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1. — — — — — SYNC2 SYNC1 SYNC0 Initial value Read/Write —...
Page 306: Timer Mode Register (Tmdr)
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously. Bit 0 SYNC0 Description Channel 0’s timer counter (16TCNT0) operates independently (Initial value) 16TCNT0 is preset and cleared independently of other channels Channel 0 operates synchronously 16TCNT0 can be synchronously preset and cleared 9.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2.
Page 307 When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction Down-Counting Up-Counting...
Page 308: Timer Interrupt Status Register A (Tisra)
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode. Bit 1 PWM1 Description Channel 1 operates normally (Initial value) Channel 1 operates in PWM mode When bit PWM1 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
Page 309 — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0 Initial value Read/Write — — R/(W)* R/(W)* R/(W)* Input capture/compare match flags A2 to A0 Status flags indicating GRA compare match or input capture Reserved bit Input capture/compare match interrupt enable A2 to A0 These bits enable or disable interrupts by the IMFA flags Reserved bit Note: * Only 0 can be written, to clear the flag.
Page 310 Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables the interrupt requested by the IMFA0 flag when IMFA0 is set to 1. Bit 4 IMIEA0 Description IMIA0 interrupt requested by IMFA0 flag is disabled (Initial value) IMIA0 interrupt requested by IMFA0 flag is enabled Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Page 311: Timer Interrupt Status Register B (Tisrb)
Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0 compare match or input capture events. Bit 0 IMFA0 Description [Clearing conditions] (Initial value) • Read IMFA0 when IMFA0 =1, then write 0 in IMFA0. • DMAC activated by IMIA0 interrupt. [Setting conditions] •...
Page 312 Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables the interrupt requested by the IMFB2 flag when IMFB2 is set to 1. Bit 6 IMIEB2 Description IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value) IMIB2 interrupt requested by IMFB2 flag is enabled Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 flag when IMFB1 is set to 1.
Page 313 Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 Description [Clearing condition] (Initial value) Read IMFB1 when IMFB1 =1, then write 0 in IMFB1. [Setting conditions] • 16TCNT1 = GRB1 when GRB1 functions as an output compare register. •...
Page 314: Timer Interrupt Status Register C (Tisrc)
9.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0 Initial value Read/Write — — R/(W)* R/(W)* R/(W)* Overflow flags 2 to 0...
Page 315 Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 flag when OVF0 is set to 1. Bit 4 OVIE0 Description OVI0 interrupt requested by OVF0 flag is disabled (Initial value) OVI0 interrupt requested by OVF0 flag is enabled Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Page 316: Timer Counters (16Tcnt)
9.2.7 Timer Counters (16TCNT) 16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel. Channel Abbreviation Function 16TCNT0 Up-counter 16TCNT1 16TCNT2 Phase counting mode: up/down-counter Other modes: up-counter Initial value Read/Write Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
Page 317: General Registers (Gra, Grb)
9.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each channel. Channel Abbreviation Function GRA0, GRB0 Output compare/input capture register GRA1, GRB1 GRA2, GRB2 Initial value Read/Write A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register.
Page 318: Timer Control Registers (16Tcr)
9.2.9 Timer Control Registers (16TCR) 16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel. Channel Abbreviation Function 16TCR0 CR controls the timer counter. The 16TCRs in all channels are 16TCR1 functionally identical. When phase counting mode is 16TCR2 selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
Page 319 Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description 16TCNT is not cleared (Initial value) 16TCNT is cleared by GRA compare match or input capture* 16TCNT is cleared by GRB compare match or input capture* Synchronous clear: 16TCNT is cleared in synchronization with other synchronized timers* Notes: 1.
Page 320: Timer I/O Control Register (Tior)
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 Function Internal clock: φ (Initial value) Internal clock: φ/2 Internal clock: φ/4 Internal clock: φ/8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input...
Page 321 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIORA and TIORC pins.
Page 322: Timer Output Level Setting Register C (Tolr)
Bit 3—Reserved: This bit cannot be modified and is always read as 1. Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 Function GRA is an output No output at compare match (Initial value)
Page 323 Bit 5—Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB Bit 5 TOB2 Description TIOCB is 0 (Initial value) TIOCB is 1 Bit 4—Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA Bit 4 TOA2 Description TIOCA...
Page 324 Bit 0—Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA Bit 0 TOA0 Description TIOCA is 0 (Initial value) TIOCA is 1...
Page 325: Cpu Interface
CPU Interface 9.3.1 16-Bit Accessible Registers The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time.
Page 326 On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 9.6 Access to Timer Counter (CPU Writes to 16TCNTH, Upper Byte) On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 9.7 Access to Timer Counter (CPU Writes to 16TCNTL, Lower Byte) On-chip data bus Module Bus interface...
Page 327: 8-Bit Accessible Registers
On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 9.9 Access to Timer Counter (CPU Reads 16TCNTL, Lower Byte) 9.3.2 8-Bit Accessible Registers The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus.
Page 328: Operation
Operation 9.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare.
Page 329 Counter setup Select counter clock Type of counting? Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter Figure 9.12 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal.
Page 330 • Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC. After the overflow, the counter continues counting up from H'0000.
Page 331 16TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 9.14 Periodic Counter Operation • 16TCNT count timing  Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Page 332  External clock source Bits TPSC2 to TPSC0 in 16TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected.
Page 333 Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
Page 334 16TCNT value H'FFFF H'0000 Time TIOCB No change No change 1 output No change No change 0 output TIOCA Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0) Figure 9.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared by compare match B.
Page 335 • Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 336 Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the DDR bit to 0 before making these TIOR settings. Select input-capture input Start counter Set the STR bit to 1 in TSTR to start the timer counter.
Page 337 • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 338: Synchronization
9.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
Page 339 Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0.
Page 340: Pwm Mode
9.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
Page 341 Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to Select counter clock select the desired edge(s) of the...
Page 342 Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible.
Page 343 Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
Page 344: Phase Counting Mode
9.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2.
Page 345 Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase counting mode. Table 9.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 346: Setting Initial Value Of 16-Bit Timer Output
9.4.6 Setting Initial Value of 16-Bit Timer Output Any desired value can be specified for the initial 16-bit timer output value when a timer count operation is started by making a setting in TOLR. Figure 9.32 shows the timing for setting the initial output value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
Page 347: Interrupts
Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR).
Page 348 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 9.34 shows the timing. φ Input capture signal 16TCNT Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture...
Page 349: Timing Of Clearing Of Status Flags
φ 16TCNT Overflow signal Figure 9.35 Timing of Setting of OVF 9.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared.
Page 350: Interrupt Sources And Dma Controller Activation
9.5.3 Interrupt Sources and DMA Controller Activation Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1.
Page 351: Usage Notes
Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 9.37.
Page 352 Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 9.38 shows the timing in this case. 16TCNT word write cycle φ...
Page 353 Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the or T state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The 16TCNT byte that was not written retains its previous value. See figure 9.39, which shows an increment pulse occurring in the T state of a byte write to 16TCNTH.
Page 354 Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 9.40. General register write cycle φ...
Page 355 Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 9.41. 16TCNT write cycle φ...
Page 356 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 9.42. General register read cycle φ GR address Address bus Internal read signal Input capture signal...
Page 357 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 358 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 9.44. General register write cycle φ...
Page 359 Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 1 and 2 are synchronized •...
Page 360 16-bit timer Operating Modes Table 9.7 (a)16-bit timer Operating Modes (Channel 0) Register Settings TSNC TMDR TIOR0 TCR0 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC0 = 1 — — PWM mode — — PWM0 = 1 —...
Page 361 Table 9.7 (b)16-bit timer Operating Modes (Channel 1) Register Settings TSNC TMDR TIOR1 TCR1 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC1 = 1 — — PWM mode — — PWM1 = 1 — Output compare A —...
Page 362 Table 9.7 (c)16-bit timer Operating Modes (Channel 2) Register Settings TSNC TMDR TIOR2 TCR2 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC2 = 1 — PWM mode — PWM2 = 1 — Output compare A —...
Page 363: Section 10 8-Bit Timers
10.1 Overview The H8/3006 and H8/3007 have a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events.
Page 364 Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources.
Page 365: Block Diagram
10.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer group 0. External clock Internal clock sources...
Page 366: Pin Configuration
10.1.3 Pin Configuration Table 10.1 summarizes the input/output pins of the 8-bit timer module. Table 10.1 8-Bit Timer Pins Group Channel Name Abbreviation I/O Input/output Timer output Output Compare match output Timer clock input TCLKC Input Counter external clock input Timer input/output TMIO Compare match output/input capture input...
Page 367: Register Configuration
10.1.4 Register Configuration Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers Channel Address*1 Name Abbreviation R/W Initial value H’FFF80 Timer control register 0 8TCR0 H’00 H’FFF82 Timer control/status register 0 8TCSR0 R/(W)* H’00 H’FFF84 Timer constant register A0 TCORA0...
Page 368: Register Descriptions
10.2 Register Descriptions 10.2.1 Timer Counters (8TCNT) 8TCNT0 8TCNT1 Initial value Read/Write 8TCNT2 8TCNT3 Initial value Read/Write The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR).
Page 369: Time Constant Registers A (Tcora)
10.2.2 Time Constant Registers A (TCORA) TCORA0 TCORA1 Initial value Read/Write TCORA2 TCORA3 Initial value Read/Write TCORA0 to TCORA3 are 8-bit readable/writable registers. The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access. The TCORA value is constantly compared with the 8TCNT value.
Page 370: Time Constant Registers B (Tcorb)
10.2.3 Time Constant Registers B (TCORB) TCORB0 TCORB1 Initial value Read/Write TCORB2 TCORB3 Initial value Read/Write TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value.
Page 371 For the timing, see section 10.4, Operation. Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt request when the CMFB flag is set to 1 in 8TCSR. Bit 7 CMIEB Description CMIB interrupt requested by CMFB is disabled (Initial value) CMIB interrupt requested by CMFB is enabled Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt...
Page 372 Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to 8TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192. The rising edge of the selected internal clock triggers the count.
Page 373: Timer Control/Status Registers (8Tcsr)
10.2.5 Timer Control/Status Registers (8TCSR) 8TCSR0 CMFB CMFA ADTE OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* 8TCSR2 CMFB CMFA — OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* — 8TCSR1, 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Page 374 Bit 6—Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA compare match or input capture. Bit 6 CMFA Description Clearing condition (Initial value) Read CMFA when CMFA = 1, then write 0 in CMFA Setting condition 8TCNT = TCORA Bit 5—Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed (H'FF →...
Page 375 Bit 4—Input Capture Enable (ICE) (8TCSR1, 8TCSR3): Selects the function of TCORB. Bit 4 Description TCORB is a compare match register (Initial value) TCORB is an input capture register Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge.
Page 376 Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A output level. Bit 1 Bit 0 Description No change when compare match A occurs (Initial value) 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) •...
Page 377: Cpu Interface
10.3 CPU Interface 10.3.1 8-Bit Registers 8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time.
Page 378 Internal data bus Module data bus interface 8TCNT0 8TCNT1 Figure 10.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1 Figure 10.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1...
Page 379: Operation
10.4 Operation 10.4.1 8TCNT Count Timing 8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected by setting bits CKS2 to CKS0 in 8TCR. Figure 10.8 shows the count timing.
Page 380: Compare Match Timing
φ External clock input 8TCNT input clock 8TCNT N–1 Figure 10.9 Count Timing for External Clock Input (When Detecting the Both Edges) 10.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Page 381: Input Capture Signal Timing
φ Compare match signal 8TCNT H'00 Figure 10.11 Timing of Clear by Compare Match Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this operation.
Page 382: Timing Of Status Flag Setting
φ Input capture input Input capture signal 8TCNT TCORB Figure 10.13 Timing of Input Capture Input Signal 10.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in 8TCSR are set to 1 by the compare match signal output when the TCOR and 8TCNT values match.
Page 383: Operation With Cascaded Connection
φ 8TCNT TCORB Input capture signal CMFB Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in this case.
Page 384 16-Bit Count Mode • Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ...
Page 385: Input Capture Setting
 Setting when Input Capture Occurs • The CMFB flag is set to 1 in 8TCR2 and 8TCR3 when the ICE bit is 1 in 8TCSR3 and input capture occurs. • TMIO pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR2.
Page 386 Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation) • Channel 1:  Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1.  Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO ) with bits OIS3 and OIS2 in 8TCSR1.
Page 387: Interrupt
10.5 Interrupt 10.5.1 Interrupt Source The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and CMIB) and overflow (OVI). Table 10.3 shows the interrupt sources and their priority order. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A separate interrupt request signal is sent to the interrupt controller by each interrupt source.
Page 388: A/D Converter Activation
10.5.2 A/D Converter Activation The A/D converter can only be activated by channel 0 compare match A. When the CMFA flag in 8TCSR0 is set to 1 and the ADTE bit is also set to 1, activation of the A/D converter will be requested on generation of channel 0 compare match A. If the TRGE bit in ADCR is set to 1 at this time, the A/D converter will be activated.
Page 389: Usage Notes
10.7 Usage Notes Note that the following kinds of contention can occur in 8-bit timer operation. 10.7.1 Contention between 8TCNT Write and Clear If a timer counter clear signal occurs in the T state of a 8TCNT write cycle, clearing of the counter takes priority and the write is not performed.
Page 390: Contention Between 8Tcnt Write And Increment
10.7.2 Contention between 8TCNT Write and Increment If an increment pulse occurs in the T state of a 8TCNT write cycle, writing takes priority and 8TCNT is not incremented. Figure 10.19 shows the timing in this case. 8TCNT write cycle φ...
Page 391: Contention Between Tcor Write And Compare Match
10.7.3 Contention between TCOR Write and Compare Match If a compare match occurs in the T state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 10.20 shows the timing in this case. TCOR write cycle φ...
Page 392: Contention Between Tcor Read And Input Capture
10.7.4 Contention between TCOR Read and Input Capture If an input capture signal occurs in the T state of a TCOR read cycle, the value before input capture is read. Figure 10.21 shows the timing in this case. TCORB read cycle φ...
Page 393: Contention Between Counter Clearing By Input Capture And Counter Increment
10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB.
Page 394: Contention Between Tcor Write And Input Capture
10.7.6 Contention between TCOR Write and Input Capture If an input capture signal occurs in the T state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 10.23 shows the timing in this case. TCOR write cycle φ...
Page 395: Contention Between 8Tcnt Byte Write And Increment In 16-Bit Count Mode (Cascaded Connection)
10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) If an increment pulse occurs in the T or T state of a 8TCNT byte write cycle in 16-bit count mode, writing takes priority and 8TCNT is not incremented. The byte data for which a write was not performed retains its previous value.
Page 396: Contention Between Compare Matches A And B
10.7.8 Contention between Compare Matches A and B If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 10.5.
Page 397 Table 10.6 Internal Clock Switchover and 8TCNT Operation CKS1 and CKS0 Write Timing 8TCNT Operation High → high switchover* Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten High → low switchover* Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten...
Page 398 CKS1 and CKS0 Write Timing 8TCNT Operation Low → low switchover* Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten Notes: 1. Including switchovers from a high clock source to the halted state, and from the halted state to a high clock source.
Page 399: Section 11 Programmable Timing Pattern Controller (Tpc)
11.1 Overview The H8/3006 and H8/3007 have a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 400: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the TPC. 16-bit timer compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output pins, group 1 PADR...
Page 401: Pin Configuration
11.1.3 Pin Configuration Table 11.1 summarizes the TPC output pins. Table 11.1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output Group 1 pulse output TPC output 5...
Page 402: Register Configuration
11.1.4 Register Configuration Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Address* Name Abbreviation Function H'EE009 Port A data direction register PADDR H'00 H'FFFD9 Port A data register PADR R/(W)* H'00 H'EE00A Port B data direction register PBDDR H'00 H'FFFDA Port B data register...
Page 403: Register Descriptions
11.2 Register Descriptions 11.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Read/Write...
Page 404: Port B Data Direction Register (Pbddr)
11.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7 to 0...
Page 405: Next Data Register A (Ndra)
11.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 406 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Page 407: Next Data Register B (Ndrb)
11.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 408 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Page 409: Next Data Enable Register A (Ndera)
11.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value Read/Write Next data enable 7 to 0 These bits enable or disable...
Page 410: Next Data Enable Register B (Nderb)
11.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 These bits enable or disable...
Page 411: Tpc Output Control Register (Tpcr)
11.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare...
Page 412 Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP to TP Bit 7 Bit 6 G3CMS1 G3CMS0 Description TPC output group 3 (TP to TP ) is triggered by compare match in 16-bit timer channel 0...
Page 413 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP to TP Bit 3 Bit 2 G1CMS1 G1CMS0 Description TPC output group 1 (TP to TP ) is triggered by compare match in 16-bit timer channel 0...
Page 414: Tpc Output Mode Register (Tpmr)
11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP to TP )
Page 415 Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for...
Page 416: Operation
11.3 Operation 11.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 417: Output Timing
11.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
Page 418: Normal Tpc Output
11.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited). Set the TPC output trigger period.
Page 419 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR • The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
Page 420: Non-Overlapping Tpc Output
11.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited). Set the TPC output trigger period in GRB Set GR values and the non-overlap margin in GRA.
Page 421 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. 16TCNT value 16TCNT H'0000 Time NDRB PBDR Non-overlap margin • The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B.
Page 422: Tpc Output Triggering By Input Capture
11.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 423: Usage Notes
11.4 Usage Notes 11.4.1 Operation of TPC Output Pins to TP are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions. When 16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output.
Page 424 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC.
Page 425: Section 12 Watchdog Timer
As a watchdog timer, it generates a reset signal for the H8/3006 and H8/3007 chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow.
Page 426: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources φ/2 RSTCSR φ/32 φ/64 Reset Reset control Clock φ/128 (internal, external) Clock φ/256 selector...
Page 427: Register Configuration
12.1.4 Register Configuration Table 12.2 summarizes the WDT registers. Table 12.2 WDT Registers Address* Write* Read Name Abbreviation Initial Value H'FFF8C H'FFF8C Timer control/status register TCSR R/(W)* H'18 H'FFF8D Timer counter TCNT H'00 H'FFF8E H'FFF8F Reset control/status register RSTCSR R/(W) * H'3F Notes: 1.
Page 428: Register Descriptions
12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable up-counter. Initial value Read/Write Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register Access. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR.
Page 429: Timer Control/Status Register (Tcsr)
12.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source Reserved bits Timer enable...
Page 430 Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value) [Setting condition] Set when TCNT changes from H'FF to H'00 Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer.
Page 431: Reset Control/Status Register (Rstcsr)
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (φ), for input to TCNT. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description φ/2 (Initial value) φ...
Page 432 Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3006 and H8/3007 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices.
Page 433: Notes On Register Access
12.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions.
Page 434 Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 435: Operation
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3006 and H8/3007 are internally reset for a duration of 518 states.
Page 436: Interval Timer Operation
12.3.2 Interval Timer Operation Figure 12.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow.
Page 437: Timing Of Setting Of Overflow Flag (Ovf)
12.3.3 Timing of Setting of Overflow Flag (OVF) Figure 12.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
Page 438: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3006 and H8/3007 chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
Page 439: Interrupts
12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 440: Section 13 Serial Communication Interface
13.1 Overview The H8/3006 and H8/3007 have a serial communication interface (SCI) with three independent channels. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 441 • Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. • The following settings can be made for the serial data to be transferred: ...
Page 442: Block Diagram
13.1.2 Block Diagram Figure 13.1 shows a block diagram of the SCI. Module data bus Internal data bus φ Baud rate φ/ 4 SCMR generator φ/16 Transmit/receive φ/64 control Parity generate Clock Parity check External clock T E I T X I R X I E R I Legend...
Page 443: Pin Configuration
13.1.3 Pin Configuration The SCI has serial pins for each channel as listed in table 13.1. Table 13.1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output Serial clock pin...
Page 444: Register Configuration
13.1.4 Register Configuration The SCI has internal registers as listed in table 13.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface.
Page 445: Register Descriptions
13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. Read/Write The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data. When one byte of data has been received, it is automatically transferred to RDR.
Page 446: Transmit Shift Register (Tsr)
13.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Read/Write The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it.
Page 447: Serial Mode Register (Smr)
13.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI’s serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator's clock source Multiprocessor mode...
Page 448 For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 Description Asynchronous mode (Initial value) Synchronous mode For smart card interface (SMIF bit in SCMR set to 1): Selects GSM mode for the smart card interface.
Page 449 Bit 4—Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in asynchronous mode.
Page 450 Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): These bits select the clock source for the on-chip baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64. For the relationship between the clock source, bit rate register setting, and baud rate, see section 13.2.8, Bit Rate Register (BRR).
Page 451: Serial Control Register (Scr)
13.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1/0 hese bits select the...
Page 452 Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 Description Transmit-data-empty interrupt request (TXI) is disabled* (Initial value) Transmit-data-empty interrupt request (TXI) is enabled Note:...
Page 453 Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 Description Receiving disabled* (Initial value) Receiving enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 454 Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): The function of these bits differs for the normal serial communication interface and for the smart card interface. Their function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the SCI clock source and enable or disable clock output from the SCK pin.
Page 455: Serial Status Register (Ssr)
For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output pin. Bit 1 Bit 0 CKE1 CKE0 Description SCK pin available for generic input/output...
Page 456 TEND MPBT TDRE RDRF ORER FER/ERS Initial value R/(W)* R/(W)* R/(W)* Read/Write R/(W)* R/(W)* Multiprocessor bit transfer Value of multiprocessor bit to be transmitted Multiprocessor bit Stores the received multiprocessor bit value Transmit end* Status flag indicating end of transmission Parity error Status flag indicating detection of a receive parity error...
Page 457 Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial data can be written in TDR. Bit 7 TDRE Description TDR contains valid transmit data [Clearing conditions] • Read TDRE when TDRE = 1, then write 0 in TDRE •...
Page 458 Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] • The chip is reset or enters standby mode •...
Page 459 For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4 Description Normal reception, no error signal* (Initial value) [Clearing conditions] •...
Page 460 For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Bit 2 TEND Description...
Page 461: Bit Rate Register (Brr)
Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value) Multiprocessor bit value in receive data is 1 Note:...
Page 462 Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) Bit Rate (bit/s) 2.097152 2.4576 Error (%) n Error (%) n Error (%) n Error (%) 141 0.03 148 -0.04 174 -0.26 212 0.03 103 0.16 108 0.21 127 0.00 155 0.16...
Page 463 φ (MHz) Bit Rate (bit/s) 6.144 7.3728 Error (%) n Error (%) n Error (%) n Error (%) 106 -0.44 108 0.08 130 -0.07 141 0.03 0.16 0.00 0.00 103 0.16 155 0.16 159 0.00 191 0.00 207 0.16 0.16 0.00 0.00 103 0.16...
Page 464 φ (MHz) Rate 14.7456 (bit/s) Error Error Error Error Error Error 2 230 -0.08 2 248 -0.17 3 64 0.70 3 70 0.03 3 79 -0.12 3 88 -0.25 2 168 0.16 2 181 0.16 2 191 0.00 2 207 0.16 2 233 0.16 3 64 0.16...
Page 465 Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode φ (MHz) Rate (bit/s) — — — — — — — — — — — — — — — — — — — — — — — — 2.5k 100k —...
Page 466 The BRR setting is calculated as follows: Asynchronous mode: φ × 10 – 1 64 × 2 × B 2n-1 Synchronous mode: φ × 10 – 1 8 × 2 × B 2n-1 B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: System clock frequency (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (For the clock sources and values of n, see the following table.)
Page 467 Table 13.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Table 13.6 and 13.7 shows the maximum bit rates with external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings φ (MHz) Maximum Bit Rate (bit/s) 62500 2.097152...
Page 468 Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 469 Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3...
Page 470: Operation
13.3 Operation 13.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. A smart card interface is also supported as a serial communication function for an IC card interface.
Page 471 Smart Card Interface • One frame consists of 8-bit data and a parity bit. • In transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of he next frame. (An elementary time unit is the time required to transmit one bit.) •...
Page 472: Operation In Asynchronous Mode
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SCR Setting SCI Transmit/Receive clock Bit 7 Bit 1 Bit 0 CKE1 CKE0 Mode Clock Source SCK Pin Function Asynchronous Internal SCI does not use the SCK pin mode Outputs clock with frequency matching the bit rate External...
Page 473 Idle (mark) state (LSB) (MSB) Serial data Start Parity Stop bit(s) Transmit or receive data 7 or 8 bits 1 bit, 1 or 2 bits 1 bit One unit of data (character or frame) none Figure 13.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits) Communication Formats: Table 13.10 shows the 12 communication formats that can be selected in asynchronous mode.
Page 474 Table 13.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP...
Page 475 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 13.9.
Page 476 Figure 13.4 shows a sample flowchart for initializing the SCI. Start of initialization Clear TE and RE bits to 0 in SCR Set the clock source in SCR. Clear the Set CKE1 and CKE0 bits in SCR (leaving TE and RE bits RIE, TIE, TEIE, MPIE, TE, and RE bits to cleared to 0) clock...
Page 477 • Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: Initialize the transmit data output function of the TxD pin is selected automatically. Start transmitting After the TE bit is set to 1, one frame of 1s is output, then transmission is possible.
Page 478 In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 479 • Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data input function of the RxD pin is selected automatically. Start receiving (2)(3) Receive error handling and break detection: if a receive error occurs, read the ORER, Read ORER, PER, and FER...
Page 480 Error handling ORER = 1 Overrun error handling FER = 1 Break? Framing error handling Clear RE bit to 0 in SCR PER = 1 Parity error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 13.7 Sample Flowchart for Receiving Serial Data (cont)
Page 481 In receiving, the SCI operates as follows: • The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 482: Multiprocessor Communication
Figure 13.8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Stop Parity Stop Data Data Idle (mark) state RDRF RXI request RXI interrupt handler Framing error, reads data in RDR and ERI request clears RDRF flag to 0 1 frame Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
Page 483 Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 13.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D...
Page 484 SCI initialization: Initialize the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT Read TDRE flag in SSR flag to 0 or 1 in SSR.
Page 485 In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 486 SCI initialization: Initialize the receive data input function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. Set MPIE bit to 1 in SCR SCI status check and ID check: read SSR, check that the RDRF flag Read ORER and FER flags is set to 1, then read data from RDR...
Page 487 Error handling ORER = 1 Overrun error handling FER = 1 Break? Clear RE bit to 0 in SCR Framing error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
Page 488: Synchronous Operation
Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value MPB detection RXI interrupt RXI interrupt handler reads Not own ID, so MPIE No RXI interrupt MPIE = 0 request...
Page 489 Figure 13.14 shows the general format in synchronous serial communication. One unit (character or frame) of transfer data Serial clock L S B Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don’t care Don’t care Note: * High except in continuous transmitting or receiving...
Page 490 Figure 13.15 shows a sample flowchart for initializing the SCI. Set the clock source in SCR. Clear the RIE, Start of initialization TIE, TEIE, MPIE, TE, and RE bits to 0. Select the communication format in SMR. Clear TE and RE bits to 0 in SCR Write the value corresponding to the bit rate in BRR.
Page 491 • Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output Initialize function selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then Read TDRE flag in SSR write transmit data in TDR and clear the...
Page 492 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 493 Initialize SCI initialization: the receive data input function of the RxD pin is selected automatically. Start receiving Receive error handling: if a receive (2)(3) error occurs, read the ORER flag in Read ORER flag in SSR SSR, then after executing the necessary error handling, clear the ORER flag to 0.
Page 494 Error handling Overrun error handling Clear ORER flag to 0 in SSR <End> Figure 13.18 Sample Flowchart for Serial Receiving (cont) In receiving, the SCI operates as follows: • The SCI synchronizes with serial clock input or output and synchronizes internally. •...
Page 495 Figure 13.19 shows an example of SCI receive operation. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt RXI interrupt handler RXI interrupt Overrun error, request reads data in RDR and request ERI interrupt clears RDRF flag to 0...
Page 496 • Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin and the read data input function of the RxD pin are selected, enabling simultaneous transmitting and Start of transmitting and receiving receiving.
Page 497: Sci Interrupts
13.4 SCI Interrupts The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR.
Page 498: Usage Notes
13.5 Usage Notes 13.5.1 Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 499 Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Page 500 The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). D – 0.5 × 100% (1 + F) ) – (L – 0.5) F – (0.5 – ..(1) Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (L = 0 to 1.0)
Page 501 TDRE Note: In operation with an external clock source, be sure that t >4 states. Figure 13.22 Example of Synchronous Transmission Using DMAC Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (high- level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
Page 502 • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Page 503: Section 14 Smart Card Interface
Section 14 Smart Card Interface 14.1 Overview An IC card (smart card) interface conforming to the ISO/IEC 7816-3 (Identification Card) standard is supported as an extension of the serial communication interface (SCI) functions. Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting.
Page 504: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCMR φ φ/4 Baud rate generator φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock Legend SCMR: Smart card mode register RSR: Receive shift register RDR:...
Page 505: Register Configuration
14.1.4 Register Configuration The smart card interface has the internal registers listed in table 14.2. The BRR, TDR, and RDR registers have their normal serial communication interface functions, as described in section 13, Serial Communication Interface. Table 14.2 Smart Card Interface Registers Channel Address* Name...
Page 506: Register Descriptions
14.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 14.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. — — — —...
Page 507 Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention cards.* The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings.
Page 508: Serial Status Register (Ssr)
14.2.2 Serial Status Register (SSR) The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND). TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)*...
Page 509 Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND, bit 2), however, are modified as follows. Bit 2 TEND Description Transmission is in progress [Clearing conditions] •...
Page 510: Serial Mode Register (Smr)
14.2.3 Serial Mode Register (SMR) The function of SMR bit 7 is modified in smart card interface mode. This change also causes a modification to the function of bits 1 and 0 in the serial control register (SCR). STOP CKS1 CKS0 Initial value Read/Write...
Page 511: Operation
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output.
Page 512: Pin Connections
14.3.2 Pin Connections Figure 14.2 shows a pin connection diagram for the smart card interface. In communication with a smart card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should both be connected to this line. The data transmission line should be pulled up to V with a resistor.
Page 513 No parity error Output from transmitting device Parity error Output from transmitting device Output from receiving Legend device Start bit D0 to D7: Data bits Parity bit Error signal Figure 14.3 Smart Card Interface Data Format The operating sequence is as follows. 1.
Page 514: Register Settings
14.3.4 Register Settings Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described in this section. Table 14.3 Smart Card Interface Register Settings Register Address Bit 7...
Page 515 The register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. Direct Convention (SDIR = SINV = O/E = 0) State With the direct convention type, the logic 0 level corresponds to state Z and the logic 1 level to state A, and transfer is performed in LSB-first order.
Page 516: Clock
14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for calculating the bit rate is shown below.
Page 517 The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. φ × 10 – 1 × B 1488 × 2 2n–1 Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0) φ...
Page 518: Transmitting And Receiving Data
14.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits to 0 in the serial control register (SCR). 2.
Page 519 For details, see Interrupt Operations and Data Transfer by DMAC in this section. Serial data Guard time (1) GM = 0 TEND 12.5 etu (2) GM = 1 TEND 11.0 etu Figure 14.4 Timing of TEND Flag Setting...
Page 520 Start Initialization Start transmitting FER/ERS = 0? Error handling TEND = 1? Write transmit data in TDR, and clear TDRE flag to 0 in SSR All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit to 0 Figure 14.5 Sample Transmission Processing Flowchart...
Page 521 (shift register) 1. Data write Data 1 2. Transfer from TDR to TSR Data 1 Data 1 Data remains in TDR Data 1 I/O signal 3. Serial data output Data 1 output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the...
Page 522 Start Initialization Start receiving ORER = 0 and PER = 0? Error handling RDRF = 1? Read RDR and clear RDRF flag to 0 in SSR All data received? Clear RE bit to 0 Figure 14.8 Sample Reception Processing Flowchart The above procedure may include interrupt handling and DMA transfer.
Page 523 Switching Modes: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been completed.
Page 524 Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources Interrupt DMAC Operating State Flag Enable Bit Source Activation Transmit Mode Normal TEND Available operation Error Not available Receive Mode Normal RDRF Available operation Error PER, ORER Not available Data Transfer by DMAC: The DMAC can be used to transmit and receive data in smart card mode, as in normal SCI operations.
Page 525 Examples of Operation in GSM Mode: When switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. • Switching from smart card interface mode to software standby mode 1. Set the P9 data register (DR) and data direction register (DDR) to the values for the fixed output state in software standby mode.
Page 526: Usage Notes
14.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate.
Page 527 From the above equation, if F = 0 and D = 0.5, the receive margin is as follows. When D = 0.5 and F = 0: M = (0.5 – 1/2 × 372) × 100% = 49.866% Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as described below.
Page 528 ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit sampling timing. 7. The TEND bit in SSR is not set for the frame for which the error signal was received. 8.
Page 529: Section 15 A/D Converter
Section 15 A/D Converter 15.1 Overview The H8/3006 and H8/3007 includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 19.6, Module Standby Function.
Page 530: Block Diagram
15.1.2 Block Diagram Figure 15.1 shows a block diagram of the A/D converter. On-chip Module data bus data bus 10-bit D/A – ø/4 Comparator Analog Control circuit multi- plexer Sample-and- ø/8 hold circuit ADTRG interrupt signal Compare match A0 ADTE 8-bit timer 8TCSR0 Legend...
Page 531: Pin Configuration
15.1.3 Pin Configuration Table 15.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter.
Page 532: Register Configuration
15.1.4 Register Configuration Table 15.2 summarizes the A/D converter’s registers. Table 15.2 A/D Converter Registers Address* Name Abbreviation Initial Value H'FFFE0 A/D data register AH ADDRAH H'00 H'FFFE1 A/D data register AL ADDRAL H'00 H'FFFE2 A/D data register BH ADDRBH H'00 H'FFFE3 A/D data register BL...
Page 533: Register Descriptions
15.2 Register Descriptions 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ADDRn — — — — — — Initial value Read/Write (n = A to D) A/D conversion data Reserved bits 10-bit data giving an A/D conversion result The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 534: A/D Control/Status Register (Adcsr)
15.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts...
Page 535 Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 Description [Clearing condition] (Initial value) • Read ADF when ADF =1, then write 0 in ADF. • DMAC activated by ADI interrupt. [Setting conditions] • Single mode: A/D conversion ends •...
Page 536 Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN Description Single mode (Initial value) Scan mode Bit 3—Clock Select (CKS): Selects the A/D conversion time.
Page 537: A/D Control Register (Adcr)
15.2.3 A/D Control Register (ADCR) TRGE — — — — — — — Initial value Read/Write — — — — — — Reserved bits Trigger enable Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by external trigger input or an 8-bit timer compare match signal.
Page 538: Cpu Interface
15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows.
Page 539: Operation
15.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 540 Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Page 541: Scan Mode (Scan = 1)
15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 542 Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels 3 AN to AN Selected)
Page 543: Input Sampling And A/D Conversion Time
15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing.
Page 544: External Trigger Input Timing
Table 15.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 545: Interrupts
15.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. The ADI interrupt request can be designated as a DMAC activation source. In this case, an interrupt request is not sent to the CPU. 15.6 Usage Notes When using the A/D converter, note the following points:...
Page 546 100 Ω to AN 0.1 µF Notes: 10 µF 0.01 µF 2. Rin: input impedance Figure 15.7 Example of Analog Input Protection Circuit Table 15.5 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance — kΩ = 4.0 V to 5.5 V and φ...
Page 547 6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3006 and H8/3007 are defined as follows: • Resolution: ....Digital output code length of A/D converter • Offset error: ....Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 15.10)
Page 548 Figure 15.10 A/D Converter Accuracy Definitions (2) 7. Allowable Signal-Source Impedance: The analog inputs of the H8/3006 and H8/3007 are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 kΩ. The reason for this rating is that it enables the input capacitor in the sample- and-hold circuit in the A/D converter to charge within the sampling time.
Page 549 H8/3006 and Equivalent circuit of H8/3007 A/D converter Sensor output impedance 10 kΩ Up to 10 kΩ Sensor input Cin = Low-pass 20 pF 15 pF filter C Up to 0.1µF Figure 15.11 Analog Input Circuit (Example)
Page 550: Section 16 D/A Converter
Section 16 D/A Converter 16.1 Overview The H8/3006 and H8/3007 include a D/A converter with two channels. 16.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20-pF capacitive load) •...
Page 551: Pin Configuration
16.1.3 Pin Configuration Table 16.1 summarizes the D/A converter's input and output pins. Table 16.1 D/A Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin Input Analog power supply and reference voltage Analog ground pin Input Analog ground and reference voltage Analog output pin 0 Output Analog output, channel 0...
Page 552: Register Descriptions
16.2 Register Descriptions 16.2.1 D/A Data Registers 0 and 1 (DADR0/1) Initial value Read/Write The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 553 Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description analog output is disabled Channel-1 D/A conversion and DA analog output are enabled Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description...
Page 554: D/A Standby Control Register (Dastcr)
16.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode. — — — — — — — DASTE Initial value Read/Write — — — — — — — Reserved bits D/A standby enable Enables or disables D/A output...
Page 555: Operation
16.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1.
Page 556 DADR0 DACR DADR0 DACR write cycle write cycle write cycle write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion result 2 Conversion High-impedance state result 1 DCONV DCONV Legend : D/A conversion time DCONV Figure 16.2 Example of D/A Converter Operation...
Page 557: D/A Output Control
16.4 D/A Output Control In the H8/3006 and H8/3007, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode. The D/A converter registers retain the values they held prior to the transition to software standby mode.
Page 558: Section 17 Ram
The on-chip RAM of the H8/3007 is assigned to addresses H'FEF20 to H'FFF1F in modes 1 and 2, and to addresses H'FFEF20 to H'FFFF1F in modes 3 and 4. The on-chip RAM of the H8/3006 are assigned to addresses H'FF720 to H'FFF1F in modes 1 and 2, and to addresses H'FFF720 to H'FFFF1F in modes 3 and 4.
Page 559: Register Configuration
17.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of SYSCR. Table 17.1 System Control Register Address* Name Abbreviation Initial Value H'EE012 System control register SYSCR H'09 Note: * Lower 20 bits of the address in advanced mode.
Page 560: System Control Register (Syscr)
17.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable bit Enables or disables on-chip RAM Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM.
Page 561: Operation
H'FFF1F in the H8/3007 in modes 1 and 2, and to addresses H'FFEF20 to H'FFFF1F in the H8/3007 in modes 3 and 4, are directed to the on-chip RAM. In the H8/3006, accesses to addresses H'FF720 to H'FFF1F in modes 1 and 2, to addresses H'FFF720 to H'FFFF1F in modes 3 and 4, are directed to the on-chip RAM.
Page 562: Section 18 Clock Pulse Generator
18.1 Overview The H8/3006 and H8/3007 have a built-in clock pulse generator (CPG) that generates the system clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (φ). The system clock is output at the φ...
Page 563: Oscillator Circuit
18.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 18.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 18.2. The damping resistance Rd should be selected according to table 18.1.
Page 564 When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B H8/3006 and H8/3007 XTAL EXTAL Figure 18.4 Example of Incorrect Board Design...
Page 565: External Clock Input
18.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF, use configuration b instead and hold the clock high in standby mode.
Page 566 External Clock: The external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. Table 18.3 shows the clock timing, figure 18.6 shows the external clock input timing, and figure 18.7 shows the external clock output settling delay timing.
Page 567 × 0.7 EXTAL × 0.5 0.3 V Figure 18.6 External Clock Input Timing STBY EXTAL φ (internal or external) DEXT RES pulse width (t Note: * t includes a 10 t DEXT RESW Figure 18.7 External Clock Output Settling Delay Timing...
Page 568: Duty Adjustment Circuit
18.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate φ. 18.4 Prescalers The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096). 18.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ).
Page 569: Usage Notes
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1. Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as follows. Bit 1 Bit 0 DIV1 DIV0 Frequency Division Ratio (Initial value) 18.5.3 Usage Notes...
Page 570: Section 19 Power-Down State
Section 19 Power-Down State 19.1 Overview The H8/3006 and H8/3007 have a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: •...
Page 571 Table 19.1 Power-Down State and Module Standby Function...
Page 572: Register Configuration
19.2 Register Configuration The H8/3006 and H8/3007 have a system control register (SYSCR) that controls the power-down state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby function. Table 19.2 summarizes these registers. Table 19.2 Control Register...
Page 573 Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description SLEEP instruction causes transition to sleep mode...
Page 574: Module Standby Control Registerh (Mstcrh)
19.2.2 Module Standby Control RegisterH (MSTCRH) MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the SCI0, SCI1, SCI2. PSTOP —...
Page 575: Module Standby Control Register L (Mstcrl)
Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby. Bit 1 MSTPH1 Description SCI1 operates normally (Initial value) SCI1 is in standby state Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby. Bit 0 MSTPH0 Description...
Page 576 Bit 6—Reserved: This bit can be written and read. Bit 5—Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in standby. Bit 5 MSTPL5 Description DRAM interface operates normally (Initial value) DRAM interface is in standby state Bit 4—Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby. Bit 4 MSTPL4 Description...
Page 577: Sleep Mode
19.3 Sleep Mode 19.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA controller (DMAC), DRAM interface, and on-chip supporting modules do not halt in sleep mode.
Page 578: Software Standby Mode
19.4 Software Standby Mode 19.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt.
Page 579: Selection Of Waiting Time For Exit From Software Standby Mode
19.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms.
Page 580: Sample Application Of Software Standby Mode
19.4.4 Sample Application of Software Standby Mode Figure 19.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 581: Hardware Standby Mode
19.5 Hardware Standby Mode 19.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, DRAM interface, and on-chip supporting modules. All modules are reset except the on-chip RAM.
Page 582: Module Standby Function
19.6 Module Standby Function 19.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1, SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently in the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL.
Page 583: System Clock Output Disabling Function
MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC. 19.7 System Clock Output Disabling Function Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the PSTOP bit is set to 1, output of the system clock halts and the φ...
Page 584: Section 20 Electrical Characteristics
Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 lists the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except for port 7) –0.3 to V +0.3 Input voltage (port 7) –0.3 to AV +0.3...
Page 585: Electrical Characteristics
20.2 Electrical Characteristics 20.2.1 DC Characteristics Tables 20.2, 20.3 and 20.4 list the DC characteristics. Table 20.4 lists the permissible output currents. Table 20.2 DC Characteristics (1) = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: V = 4.5 V to AV = AV = 0 V*...
Page 586 Item Symbol Unit Test Conditions µA STBY, NMI, Input leakage — — = 0.5 V to RES, current – 0.5 V to MD µA Port 7 — — = 0.5 V to – 0.5 V µA Three-state Ports 4, 6, —...
Page 587 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that V min = V – 0.5 V and V max = 0.5 V. ×...
Page 588 Table 20.3 DC Characteristics (2) Conditions: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 589 Item Symbol Unit Test Conditions µA STBY, NMI, Input leakage — — = 0.5 V to RES, current – 0.5 V to MD µA Port 7 — — = 0.5 V to – 0.5 V µA Three-state Ports 4, 6, —...
Page 590 Connect the AV and V pins to the V and connect the AV pin to the V respectively. 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that V min = V –...
Page 591 Table 20.4 DC Characteristics (3) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 592 Item Symbol Unit Test Conditions µA STBY, NMI, Input leakage — — = 0.5 V to RES, current – 0.5 V to MD µA Port 7 — — = 0.5 V to – 0.5 V µA Three-state Ports 4, 6, 8 to —...
Page 593 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that V min = V – 0.5 V and V max = 0.5 V. ×...
Page 594 Notes: 1. To protect chip reliability, do not exceed the output current values in table 20.5. 2. When driving a darlington pair, always insert a current-limiting resistor in the output line, as shown in figures 20.1. H8/3006 and H8/3007 2 kΩ Port Darlington pair Figure 20.1 Darlington Pair Drive Circuit (Example)
Page 595: Ac Characteristics
20.2.2 AC Characteristics Clock timing parameters are listed in table 20.6, control signal timing parameters in table 20.7, and bus timing parameters in table 20.8. Timing parameters of the on-chip supporting modules are listed in table 20.9. Table 20.6 Clock Timing Condition: T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range...
Page 596 Table 20.7 Control Signal Timing Condition: T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V, φ...
Page 597 Table 20.8 Bus Timing Condition: T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V, φ...
Page 598 Condition Test Item Symbol Min Unit Conditions Write data setup 1.0 t — 1.0 t — 1.0 t — Figure 20.8, WDS1 time 1 – 50 – 40 – 30 figure 20.9, figure 20.11, Write data setup 2.0 t — 2.0 t —...
Page 599 Condition Test Item Symbol Min Unit Conditions CAS delay time 1 t — — — Figure 20.14 CASD1 figure 20.16 CAS delay time 2 t — — — CASD2 WE delay time — — — CAS pulse width 1.5 t —...
Page 600 Table 20.9 Timing of On-Chip Supporting Modules Condition: T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V, φ...
Page 601 Condition Test Item Symbol Unit Conditions Input Asyn- — — — Figure 20.20 Scyc clock chronous cycle Syn- — — — chronous Input clock rise — — — SCKr time Input clock fall — — — SCKf time Input clock SCKW Scyc pulse width...
Page 602 C = 90 pF: Ports 4, 6, 8, A to A to D H8/3006 and C = 30 pF: Ports 9, A, B, RESO H8/3007 Ω R = 2.4 k output pin Ω R = 12 k Input/output timing measurement levels •...
Page 603: A/D Conversion Characteristics
20.2.3 A/D Conversion Characteristics Table 20.10 lists the A/D conversion characteristics. Table 20.10 A/D Conversion Characteristics Condition: T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV...
Page 604 Condition Item Min Typ Max Min Typ Max Min Typ Max Unit Conver- Resolution bits sion time: Conversion time (single — — — — — — 70 states mode) Analog input capacitance — — — — — — φ ≤ 13 MHz — Permissible —...
Page 605: D/A Conversion Characteristics
20.2.4 D/A Conversion Characteristics Table 20.11 lists the D/A conversion characteristics. Table 20.11 D/A Conversion Characteristics Condition: T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV...
Page 606: Operational Timing
20.3 Operational Timing This section shows timing diagrams. 20.3.1 Clock Timing Clock timing is shown as follows: • System clock timing Figure 20.3 shows the system clock timing. • Oscillator settling timing Figure 20.4 shows the oscillator settling timing. φ Figure 20.3 System Clock Timing φ...
Page 607: Control Signal Timing
20.3.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 20.5 shows the reset input timing. • Reset output timing Figure 20.6 shows the reset output timing. • Interrupt input timing Figure 20.7 shows the interrupt input timing for NMI and IRQ to IRQ φ...
Page 608 φ NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0 to 5) NMIW (j = 0 to 5) Figure 20.7 Interrupt Input Timing...
Page 609: Bus Timing
20.3.3 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 20.8 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 20.9 shows the timing of the external three-state access cycle. •...
Page 610 φ to A PCH1 ACC3 ACC3 PCH2 (read) ACC1 to D (read) PCH1 HWR, LWR (write) WSW1 WDS1 to D (write) , CSn, and RD. Note: Specification from the earliest negation timing of A to A Figure 20.8 Basic Bus Cycle: Two-State Access...
Page 611 φ to A ACC4 ACC4 (read) ACC2 to D (read) WSW2 HWR, LWR (write) WDS2 to D (write) Figure 20.9 Basic Bus Cycle: Three-State Access...
Page 612 φ to A RD (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 20.10 Basic Bus Cycle: Three-State Access with One Wait State...
Page 613 φ to A to A ACC4 ACC4 ACC1 ACC2 to D , CSn, and RD. Note: Specification from the earliest negation timing of A to A Figure 20.11 Burst ROM Access Timing: Two-State Access...
Page 614 φ to A to A ACC4 ACC4 ACC2 ACC2 to D , CSn, and RD. Note: Specification from the earliest negation timing of A to A Figure 20.12 Burst ROM Access Timing: Three-State Access φ BRQS BRQS BREQ BACD2 BACD1 BACK to A AS, RD,...
Page 615: Dram Interface Bus Timing
20.3.4 DRAM Interface Bus Timing DRAM interface bus timing is shown as follows: • DRAM bus timing: read and write access Figure 20.14 shows the timing of the read and write access. • DRAM bus timing: CAS before RAS refresh Figure 20.15 shows the timing of the CAS before RAS refresh.
Page 616 φ to A RAD2 to CS to RAS (RAS RAD1 CASD2 CAS1 UCAS, LCAS (read) RD (WE) (High) (read) RDH* to D (read) CASD1 CASD2 CAS2 UCAS, LCAS (write) RD (WE) (write) to D (write) RFSH (High) Note: * Specification from the earliest negation timing of RAS and CAS. Figure 20.14 DRAM Bus Timing (Read/Write)
Page 617 φ RAD1 RAD2 to CS (RAS CASD1 CASD2 CSR1 UCAS, CAS3 LCAS RD (WE) (High) RAD2 RAD1 CSR1 RFSH Figure 20.15 DRAM Bus Timing (CAS Before RAS Refresh)
Page 618: Tpc And I/O Port Timing
φ CSR2 to CS (RAS UCAS, LCAS RD (WE) (High) CSR2 RFSH Figure 20.16 DRAM Bus Timing (Self-Refresh) 20.3.5 TPC and I/O Port Timing Figure 20.17 shows the TPC and I/O port input/output timing. φ Port 4, 6 to B (read) Port 4, 6, 8 to B...
Page 619: Timer Input/Output Timing
20.3.6 Timer Input/Output Timing ITU timing is shown as follows: • Timer input/output timing Figure 20.18 shows the timer input/output timing. • Timer external clock input timing Figure 20.19 shows the timer external clock input timing. φ TOCD Output compare TICS Input capture...
Page 620: Sci Input/Output Timing
20.3.7 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 20.20 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 20.21 shows the SCI input/output timing in synchronous mode. SCKW SCKr SCKf to SCK...
Page 621: Dmac Timing
20.3.8 DMAC Timing DMAC timing is shown as follows. • DMAC TEND output timing for 2 state access Figure 20.22 shows the DMAC TEND output timing for 2 state access. • DMAC TEND output timing for 3 state access Figure 20.23 shows the DMAC TEND output timing for 3 state access. •...
Page 622: Appendix A Instruction Set
Appendix A Instruction Set Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand Program counter...
Page 623 Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes...
Page 624 Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — Rs8 → Rd8 MOV.B Rs, Rd —...
Page 625 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z @aa:24 → Rd16 MOV.W @aa:24, Rd — — 0 — Rs16 → @ERd MOV.W Rs, @ERd — — 0 — Rs16 → @(d:16, ERd) MOV.W Rs, @(d:16, —...
Page 626 — — 0 — ERn32 → @SP MOVFPE @aa:16, Cannot be used in the Cannot be used in the H8/3006 and H8/3007 H8/3006 and H8/3007 MOVTPE Rs, Cannot be used in the Cannot be used in the @aa:16 H8/3006 and H8/3007 H8/3006 and H8/3007 2.
Page 627 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32 INC.L #1, ERd — — — ERd32+2 → ERd32 INC.L #2, ERd — — — DAA Rd Rd8 decimal adjust — * * —...
Page 628 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32 ÷ Rs16 → ERd32 DIVXU. W Rs, ERd — — (6) (7) — — (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷ Rs8 → Rd16 DIVXS.
Page 629 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — 0 — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — 0 — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
Page 630 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd — — SHAR.L ERd —...
Page 631 5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 632 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬(#xx:3 of Rd8) →...
Page 633 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Condition H N Z BRA d:8 (BT d:8) — If condition Always — — — — — — is true then BRA d:16 (BT d:16) —...
Page 634 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Operation Condition H N Z Z ∨ (N⊕V) = 0 BLE d:8 — If condition — — — — — — is true then Z ∨ (N⊕V) = 1 BLE d:16 —...
Page 635 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z PC → @–SP TRAPA #x:2 — 1 — — — — — 14 16 CCR → @–SP <vector> → PC CCR ←...
Page 636 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. For other cases see section A.3, Normal mode is not available in the H8/3006 and H8/3007. 2. n is the value set in register R4L or R4.
Page 637: Operation Code Map
Operation Code Map (1)
Page 638 Operation Code Map (2)
Page 639 Operation Code Map (3)
Page 640: Number Of States Required For Execution
Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states required per cycle according to the bus size.
Page 641 Table A.3 Number of States per Cycle Access Conditions External Device On-Chip Sup- porting Module 8-Bit Bus 16-Bit Bus Cycle On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S Stack operation Byte data access...
Page 642 Table A.4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, Erd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd ADDX...
Page 643 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16...
Page 644 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3, BNOT #xx:3, @Erd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Erd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Erd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd...
Page 645 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B 2n + 2* EEPMOV.W...
Page 646 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd...
Page 647 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOVFPE MOVFPE @aa:16, Rd* MOVTPE MOVTPE Rs, @aa:16* MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd...
Page 648 XOR.L #xx:32, Erd XOR.L ERs, ERd XORC XORC #xx:8, CCR Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. 2. Not available in the H8/3006 and H8/3007.
Page 649: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Addresses Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'EE000 Reserved area (access prohibited) H'EE001 H'EE002 H'EE003 P4DDR DDR P4 DDR P4...
Page 650 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'EE020 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller H'EE021 ASTCR AST7 AST6 AST5...
Page 651 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'FFF20 MAR0AR DMAC channel 0A H'FFF21 MAR0AE H'FFF22 MAR0AH H'FFF23 MAR0AL H'FFF24 ETCR0AH 8 H'FFF25 ETCR0AL 8 H'FFF26...
Page 652 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'FFF40 — — — — — — — — — H'FFF41 — — — —...
Page 653 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'FFF60 TSTR — — — — — STR2 STR1 STR0 16-bit timer, (all channels) H'FFF61 TSNC —...
Page 654 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'FFF80 8TCR0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8-bit timer channels 0 H'FFF81 8TCR1 CMIEB CMIEA...
Page 655 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'FFFA0 TPMR — — — — G3NOV G2NOV G1NOV G0NOV H'FFFA1 TPCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 H'FFFA2 NDERB NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8...
Page 656 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'FFFC0 STOP CKS1 CKS0 channel 2 H'FFFC1 H'FFFC2 MPIE TEIE CKE1 CKE0 H'FFFC3 H'FFFC4 TDRE RDRF ORER...
Page 657 Data Register Name Address Register Module (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name H'FFFE0 ADDRAH 8 converter H'FFFE1 ADDRAL 8 — — — — — — H'FFFE2 ADDRBH 8 H'FFFE3 ADDRBL 8...
Page 658: Functions
Functions Register abbreviation Address to which register is mapped Register name Name of on-chip supporting module TIER—Timer Interrupt Enable Register H' 90 Bit numbers ICIAE ICIBE ICICE OCIDE OCIAE OCIBE OVIE Initial bit values Names of the bits. Initial value Dashes (—) indicate R/W: reserved bits.
Page 659 P4DDR—Port 4 Data Direction Register H'EE003 Port 4 Initial value Read/Write Port 4 input/output select Generic input Generic output P6DDR—Port 6 Data Direction Register H'EE005 Port 6 — Initial value — Read/Write Port 6 input/output select Generic input Generic output...
Page 660 P8DDR—Port 8 Data Direction Register H'EE007 Port 8 Initial value Modes 1 to 4 Read/Write Port 8 input/output select Generic input Generic output Port 8 input/output select Generic input CS output...
Page 661 P9DDR—Port 9 Data Direction Register H'EE008 Port 9 Initial value Read/Write Port 9 input/output select Generic input Generic output PADDR—Port A Data Direction Register H'EE009 Port A Initial value Modes 3, 4 Read/Write Initial value Modes 1, 2 Read/Write Port A input/output select Generic input pin Generic output pin PBDDR—Port B Data Direction Register...
Page 662 MDCR—Mode Control Register H'EE011 System control MDS2 MDS1 MDS0 Initial value Read/Write Mode select 2 to 0 Bit 2 Bit 1 Bit 0 Operating Mode Mode 1 Mode 2 Mode 3 Mode 4 Note: * Determined by the state of the mode pins (MD2 to MD0).
Page 663 SYSCR—System Control Register H'EE012 System control SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable On-chip RAM is disabled On-chip RAM is enabled Software standby output port enable In software standby mode, all address bus and bus control signals are high- impedance In software standby mode,...
Page 664 BRCR—Bus Release Control Register H'EE013 Bus controller A23E A22E A21E A20E BRLE Modes Initial value 1, 2 Read/Write Modes Initial value 3, 4 Read/Write Bus release enable Address 23 to 20 enable The bus cannot be Address output released to an Other input/output external device The bus can be...
Page 665 IER—IRQ Enable Register H'EE015 Interrupt Controller IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write to IRQ enable to IRQ interrupts are disabled to IRQ interrupts are enabled ISR—IRQ Status Register H'EE016 Interrupt Controller IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write R/(W)*...
Page 666 IPRA—Interrupt Priority Register A H'EE018 Interrupt Controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 Priority level 0 (low priority) Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 667 DASTCR—D/A Standby Control Register H'EE01A D/A converter DASTE Initial value Read/Write D/A standby enable D/A output is disabled in software standby mode (Initial value) D/A output is enabled in software standby mode...
Page 668 DIVCR—Division Control Register H'EE01B System control DIV1 DIV0 Initial value Read/Write Divide 1 and 0 Bit 1 Bit 0 Frequency Division Ratio DIV1 DIV0 (Initial value)
Page 669 MSTCRH—Module Standby Control Register H H'EE01C System control PSTOP MSTPH2 MSTPH1 MSTPH0 Initial value Read/Write Module standby H2 to H0 Selection bits for placing modules in standby state. Reserved bits φ clock stop Enables or disables ø clock output. MSTCRL—Module Standby Control Register L H'EE01D System control MSTPL7...
Page 670 CSCR—Chip Select Control Register H'EE01F Bus controller CS7E CS6E CS5E CS4E Initial value Read/Write Chip select 7 to 4 enable Bit n Description CSnE Output of chip select signal CSn is disabled (Initial value) Output of chip select signal CSn is enabled (n = 7 to 4)
Page 671 ABWCR—Bus Width Control Register H'EE020 Bus controller ABW2 ABW1 ABW0 ABW7 ABW6 ABW5 ABW4 ABW3 Modes 1, 3 Initial value Modes 2, 4 Initial value Read/Write Area 7 to 0 bus width control Bits 7 to 0 Bus Width of Access Area ABW7 to ABW0 Areas 7 to 0 are 16-bit access areas...
Page 672 WCRH—Wait Control Register H H'EE022 Bus controller Initial value Read/Write Area 4 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 5 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 673 WCRL—Wait Control Register L H'EE023 Bus controller Initial value Read/Write Area 0 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 1 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 674 BCR—Bus Control Register H'EE024 Bus controller ICIS1 ICIS0 BROME BRSTS1 BRSTS0 — RDEA WAITE Initial value Read/Write — Wait pin enable WAIT pin wait input is disabled WAIT pin wait input is enabled Area division unit select Area divisions are as follows: Area 0: 2 Mbytes Area 4: 1.93 Mbytes Area 1: 2 Mbytes Area 5: 4 kbytes Area 2: 8 Mbytes Area 6: 23.75 kbytes...
Page 675 DRCRA—DRAM Control Register A H'EE026 DRAM interface DRAS2 DRAS1 DRAS0 SRFMD RFSHE Initial value Read/Write Refresh pin enable RFSH pin refresh signal output is disabled RFSH pin refresh signal output is enabled Self-refresh mode DRAM self-refreshing is disabled in software standby mode DRAM self-refreshing is enabled in software standby mode RAS down mode...
Page 676 DRCRB—DRAM Control Register B H'EE027 DRAM interface MXC1 MXC0 CSEL RCYCE Initial value Read/Write Refresh cycle wait control Wait state (T ) insertion is disabled 1 wait state (T ) is inserted RAS-CAS wait Wait state (T ) insertion is disabled 1 wait state (T ) is inserted TP cycle control...
Page 677 RTMCSR—Refresh Timer Control/Status Register H'EE028 DRAM interface CMIE CKS2 CKS1 CKS0 Initial value Read/Write R/(W)* Refresh counter clock select CKS2 CKS1 CKS0 Description Count operation halted φ/2 used as counter clock φ/8 used as counter clock φ/32 used as counter clock φ/128 used as counter clock φ/512 used as counter clock φ/2048 used as counter clock...
Page 678 RTCNT—Refresh Timer Counter H'EE029 DRAM interface Initial value Read/Write Incremented by internal clock selected by bits CKS2 to CKS0 in RTMCSR RTCOR—Refresh Time Constant Register H'EE02A DRAM interface Initial value Read/Write RTCNT compare match period Note: Only byte access should be used with this register.
Page 679 P4PCR—Port 4 Input Pull-Up Control Register H'EE03E Port 4 Initial value Read/Write Port 4 input pull-up control 7 to 0 Input pull-up transistor is off Input pull-up transistor is on Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input).
Page 680 ETCR0A H/L—Execute Transfer Count Register 0A H/L H'FFF24 H'FFF25 DMAC0 • Short address mode  I/O mode and idle mode Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter  Repeat mode Undetermined Undetermined Initial value...
Page 681 IOAR0A—I/O Address Register 0A H'FFF26 DMAC0 Undetermined Initial value Read/Write Short address mode : source or destination address Full address mode : not used...
Page 682 DTCR0A—Data Transfer Control Register 0A H'FFF27 DMAC0 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 Data Transfer Activation Source DTS2 DTS1 DTS0 Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1...
Page 683 DTCR0A—Data Transfer Control Register 0A (cont) H'FFF27 DMAC0 • Full address mode DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Initial value Read/Write Data transfer select 0A Normal mode Block transfer mode Data transfer select 2A and 1A Set both bits to 1 Data transfer interrupt enable Interrupt requested by DTE bit is disabled Interrupt requested by DTE bit is enabled...
Page 684 MAR0B R/E/H/L—Memory Address Register 0B R/E/H/L H'FFF28 H'FFF29 DMAC0 H'FFF2A H'FFF2B Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W MAR0BR MAR0BE Undetermined Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0BH MAR0BL Source or destination address...
Page 685 ETCR0B H/L—Execute Transfer Count Register 0B H/L H'FFF2C, H'FFF2D DMAC0 • Short address mode  I/O mode and idle mode Undetermined Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Transfer counter  Repeat mode Undetermined Undetermined Initial value...
Page 686 IOAR0B—I/O Address Register 0B H'FFF2E DMAC0 Undetermined Initial value Read/Write Short address mode : source or destination address Full address mode : not used...
Page 687 DTCR0B—Data Transfer Control Register 0B H'FFF2F DMAC0 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 Data Transfer Activation Source DTS2 DTS1 DTS0 Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1...
Page 688 DTCR0B—Data Transfer Control Register 0B (cont) H'FFF2F DMAC0 • Full address mode DTS0B DTME DAID DAIDE DTS2B DTS1B Initial value Read/Write Data transfer select 2B to 0B Data transfer master enable Bit 2 Bit 1 Bit 0 Data Transfer Activation Source Data transfer is disabled DTS2B DTS1B...
Page 689 MAR1A R/E/H/L—Memory Address Register 1A R/E/H/L H'FFF30 H'FFF31 DMAC1 H'FFF32 H'FFF33 Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W MAR1AR MAR1AE Undetermined Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1AH MAR1AL Note: Bit functions are the same as for DMAC0.
Page 690 IOAR1A—I/O Address Register 1A H'FFF36 DMAC1 Undetermined Initial value Read/Write Note: Bit functions are the same as for DMAC0. DTCR1A—Data Transfer Control Register 1A H'FFF37 DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write • Full address mode DTSZ SAID...
Page 691 MAR1B R/E/H/L—Memory Address Register 1B R/E/H/L H'FFF38 H'FFF39 DMAC1 H'FFF3A H'FFF3B Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W MAR1BR MAR1BE Undetermined Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1BH MAR1BL Note: Bit functions are the same as for DMAC0.
Page 692 IOAR1B—I/O Address Register 1B H'FFF3E DMAC1 Undetermined Initial value Read/Write Note: Bit functions are the same as for DMAC0. DTCR1B—Data Transfer Control Register 1B H'FFF3F DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write • Full address mode DTME DAID...
Page 693 TSTR—Timer Start Register H'FFF60 16-Bit Timer (Common) STR2 STR1 STR0 Initial value Read/Write Reserved bits Counter start 0 16TCNT0 count halted (Initial value) 16TCNT0 counting Counter start 1 16TCNT1 count halted (Initial value) 16TCNT1 counting Counter start 2 16TCNT2 count halted (Initial value) 16TCNT2 countIng...
Page 694 TSNC—Timer Syncro Register H'FFF61 16-Bit Timer (Common) SYNC2 SYNC1 SYNC0 Initial value Read/Write Reserved bits Timer sync 0 Channel 0 timer counter (16TCNT0) operates independently (16TCNT0 presetting/clearing unrelated to other channels) (Initial value) Channel 0 operates synchronously 16TCNT0 synchronous presetting/synchronous clearing possible Timer sync 1 Channel 1 timer counter (16TCNT1) operates independently (16TCNT1 presetting/clearing unrelated to other channels)
Page 695 TMDR—Timer Mode Register H'FFF62 16-Bit Timer (Common) FDIR PWM2 PWM1 PWM0 Initial value Read/Write PWM mode 0 Normal operation selected for channel 0 (Initial value) PWM mode selected for channel 0 PWM mode 1 Normal operation selected for channel 1 (Initial value) PWM mode selected for channel 1 PWM mode 2...
Page 696 TOLR—Timer Output Level Setting Register H'FFF63 16-Bit Timer (Common) TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value Read/Write Output level setting A0 TIOCA0 set to 0 output (Initial value) TIOCA0 set to 1 output Output level setting B0 TIOCB0 set to 0 output (Initial value) TIOCB0 set to 1 output Output level setting A1...
Page 697 TISRA—Timer Interrupt Status Register A H'FFF64 16-Bit Timer (Common) IMIEA2 IMIEA1 IMIEA0 IMFA2 IMFA1 IMFA0 Initial value Read/Write R/(W)* R/(W)* R/(W)* Input capture/compare match flag A0 [Clearing conditions] (Initial value) • Read IMFA0 when IMFA0 =1, then write 0 in IMFA0 •...
Page 698 TISRB—Timer Interrupt Status Register B H'FFF65 16-Bit Timer (Common) IMIEB2 IMIEB1 IMIEB0 IMFB2 IMFB1 IMFB0 Initial value Read/Write R/(W)* R/(W)* R/(W)* Input capture/compare match flag B0 [Clearing condition] (Initial value) Read IMFB0 when IMFB0 =1, then write 0 in IMFB0 [Setting conditions] •...
Page 699 TISRC—Timer Interrupt Status Register C H'FFF66 16-Bit Timer (Common) OVIE2 OVIE1 OVIE0 OVF2 OVF1 OVF0 Initial value Read/Write R/(W)* R/(W)* R/(W)* Overflow flag 0 [Clearing condition] (Initial value) Read OVF0 when OVF0 =1, then write 0 in OVF0 [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000 Overflow flag 1 [Clearing condition]...
Page 700 16TCR0—Timer Control Register 0 H'FFF68 16-Bit Timer Channel 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 Description TPSC2 TPSC1 TPSC0 Internal clock: Counts on φ (Initial value) Internal clock: Counts on φ/2 Internal clock: Counts on φ/4 Internal clock: Counts on φ/8...
Page 701 TIOR0—Timer I/O Control Register 0 H'FFF69 16-Bit Timer Channel 0 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Initial value Read/Write I/O control A2 to A0 Bit 2 Bit 1 Bit 0 Description IOA2 IOA1 IOA0 GRA is output Pin output at compare match disabled (Initial value) compare register 0 output at GRA compare match 1 output at GRA compare match...
Page 702 16TCNT0H/L—Timer Counter 0H/L H'FFF6A 16-Bit Timer Channel 0 H'FFF6B Initial value Read/Write Up-counter GRA0H/L—General Register A0 H/L H'FFF6C 16-Bit Timer Channel 0 H'FFF6D Initial value Read/Write Output compare/input capture dual-function register GRB0H/L—General Register B0 H/L H'FFF6E 16-Bit Timer Channel 0 H'FFF6F Initial value Read/Write...
Page 703 16TCR1—Timer Control Register 1 H'FFF70 16-Bit Timer Channel 1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0. TIOR1—Timer I/O Control Register 1 H'FFF71 16-Bit Timer Channel 1 IOB2 IOB1 IOB0...
Page 704 GRA1H/L—General Register A1 H/L H'FFF74 16-Bit Timer Channel 1 H'FFF75 Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0. GRB1H/L—General Register B1 H/L H'FFF76 16-Bit Timer Channel 1 H'FFF77 Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0. 16TCR2—Timer Control Register 2 H'FFF78 16-Bit Timer Channel 2...
Page 705 TIOR2—Timer I/O Control Register 2 H'FFF79 16-Bit Timer Channel 2 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0. 16TCNT2H/L—Timer Counter 2H/L H'FFF7A 16-Bit Timer Channel 2 H'FFF7B Initial value Read/Write Phase counting mode: Up/down-counter...
Page 706 GRB2H/L—General Register B2 H/L H'FFF7E 16-Bit Timer Channel 2 H'FFF7F Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0.
Page 707 8TCR0—Timer Control Register 0 H'FFF80 8-bit timer channel 0 8TCR1—Timer Control Register 1 H'FFF81 8-bit timer channel 1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 Clock input is disabled Internal clock, counted on rising edge of φ/8 Internal clock, counted on rising edge of φ/64...
Page 708 8TCSR0—Timer Control/Status Register 0 H'FFF82 8-bit timer channel 0 CMFB CMFA ADTE OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A...
Page 709 8TCSR1—Timer Control/Status Register 1 H'FFF83 8-bit timer channel 1 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A...
Page 710 TCORA0—Timer Constant Register A0 H'FFF84 8-bit timer channel 0 TCORA1—Timer Constant Register A1 H'FFF85 8-bit timer channel 1 TCORA0 TCORA1 Initial value Read/Write TCORB0—Timer Constant Register B0 H'FFF86 8-bit timer channel 0 TCORB1—Timer Constant Register B1 H'FFF87 8-bit timer channel 1 TCORB0 TCORB1 Initial value...
Page 711 TCSR—Timer Control/Status Register H'FFF8C WT/IT CKS2 CKS1 CKS0 Initial value Read/Write R/(W)* Clock select 2 to 0 CKS2 CKS1 CKS0 Description φ/2 φ/32 φ/64 φ/128 φ/256 φ/512 φ/2048 φ/4096 Timer enable Timer disabled • TCNT is initialized to H'00 and halted Timer enabled •...
Page 712 TCNT—Timer Counter H'FFF8D (read), H'FFF8C (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'FFF8F (read), H'FFF8E (write) WRST RSTOE Initial value Read/Write R/(W)* Reset output enable External output of reset signal is disabled External output of reset signal is enabled Watchdog timer reset [Clearing conditions] •...
Page 713 8TCR2—Timer Control Register 2 H'FFF90 8-bit timer channel 2 8TCR3—Timer Control Register 3 H'FFF91 8-bit timer channel 3 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 CKS2 CKS1 CKS0 Description Clock input is disabled Internal clock, counted on rising edge of φ/8 Internal clock, counted on rising edge...
Page 714 8TCSR2—Timer Control/Status Register 2 H'FFF92 8-bit timer channel 2 8TCSR3—Timer Control/Status Register 3 H'FFF93 8-bit timer channel 3 8TCSR2 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* — 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1...
Page 715 TCORA2—Timer Constant Register A2 H'FFF94 8-bit timer channel 2 TCORA3—Timer Constant Register A3 H'FFF95 8-bit timer channel 3 TCORA2 TCORA3 Initial value Read/Write TCORB2—Timer Constant Register B2 H'FFF96 8-bit timer channel 2 TCORB3—Timer Constant Register B3 H'FFF97 8-bit timer channel 3 TCORB2 TCORB3 Initial value...
Page 716 DADR0—D/A Data Register 0 H'FFF9C Initial value Read/Write D/A conversion data DADR1—D/A Data Register 1 H'FFF9D Initial value Read/Write D/A conversion data...
Page 717 DACR—D/A Control Register H'FFF9E DAOE1 DAOE0 Initial value Read/Write D/A enable Bit 7 Bit 6 Bit 5 Description DAOE1 DAOE0 D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1...
Page 718 TPMR—TPC Output Mode Register H'FFFA0 G3NOV G2NOV G1NOV G0NOV Initial value Read/Write Group 0 non-overlap Normal TPC output in group 0. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected 16-bit timer channel Group 1 non-overlap...
Page 719 TPCR—TPC Output Control Register H'FFFA1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 16-Bit Timer Channel Selected as Output Trigger G0CMS1 G0CMS0 TPC output group 0 (TP to TP ) is triggered by compare match in 16-bit timer channel 0...
Page 720 NDERB—Next Data Enable Register B H'FFFA2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 Description NDER15 to NDER8 TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB TPC outputs TP to TP...
Page 721 NDRB—Next Data Register B H'FFFA4/H'FFFA6 • Same trigger for TPC output groups 2 and 3  Address H'FFFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Store the next output data for TPC output group 3 Store the next output data for TPC output group 2 ...
Page 722 NDRA—Next Data Register A H'FFFA5/H'FFFA7 • Same trigger for TPC output groups 0 and 1  Address H'FFFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Store the next output data for TPC output group 1 Store the next output data for TPC output group 0 ...
Page 723 SMR—Serial Mode Register H'FFFB0 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 Clock Source CKS1 CKS0 φ clock φ/4 clock φ/16 clock φ/64 clock Multiprocessor mode Multiprocessor function disabled Multiprocessor function enabled Stop bit length One stop bit Two stop bits...
Page 724 BRR—Bit Rate Register H'FFFB1 SCI0 Initial value Read/Write Serial communication bit rate setting...
Page 725 SCR—Serial Control Register H'FFFB2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Receive enable (for serial communication interface) Receiving is Bit 1 Bit 0 disabled Description CKE1 CKE0 Receiving is Internal clock, SCK pin Asynchronous mode enabled available for generic I/O Internal clock, SCK pin...
Page 726 TDR—Transmit Data Register H'FFFB3 SCI0 Initial value Read/Write Serial transmit data...
Page 727 SSR—Serial Status Register H'FFFB4 SCI0 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor bit transfer Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 Multiprocessor bit Multiprocessor bit value in receive data is 0 Multiprocessor bit value in receive data is 1 Transmit end (for serial communication interface)
Page 728 RDR—Receive Data Register H'FFFB5 SCI0 Initial value Read/Write Serial receive data...
Page 729 SCMR—Smart Card Mode Register H'FFFB6 SCI0 SDIR SINV SMIF Initial value Read/Write Smart card interface mode select Smart card interface function is disabled (Initial value) Smart card interface function is enabled Smart card data invert Unmodified TDR contents are transmitted (Initial value) Receive data is stored unmodified in RDR Inverted TDR contents are transmitted...
Page 730 SMR—Serial Mode Register H'FFFB8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H'FFFB9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H'FFFBA SCI1 MPIE...
Page 731 TDR—Transmit Data Register H'FFFBB SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SSR—Serial Status Register H'FFFBC SCI1 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag.
Page 732 SCMR—Smart Card Mode Register H'FFFBE SCI1 SDIR SINV SMIF Initial value Read/Write Note: Bit functions are the same as for SCI0.
Page 733 SMR—Serial Mode Register H'FFFC0 SCI2 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H'FFFC1 SCI2 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H'FFFC2 SCI2 MPIE...
Page 734 TDR—Transmit Data Register H'FFFC3 SCI2 Initial value Read/Write Note: Bit functions are the same as for SCI0. SSR—Serial Status Register H'FFFC4 SCI2 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag.
Page 735 SCMR—Smart Card Mode Register H'FFFC6 SCI2 SDIR SINV SMIF Initial value Read/Write Note: Bit functions are the same as for SCI0.
Page 736 P4DR—Port 4 Data Register H'FFFD3 Port 4 Initial value Read/Write Data for port 4 pins P6DR—Port 6 Data Register H'FFFD5 Port 6 Initial value Read/Write Data for port 6 pins Note: * Determined by pin P6...
Page 737 P7DR—Port 7 Data Register H'FFFD6 Port 7 Initial value Read/Write Data for port 7 pins Note: * Determined by pins P7 to P7 P8DR—Port 8 Data Register H'FFFD7 Port 8 Initial value Read/Write Data for port 8 pins...
Page 738 P9DR—Port 9 Data Register H'FFFD8 Port 9 Initial value Read/Write Data for port 9 pins PADR—Port A Data Register H'FFFD9 Port A Initial value Read/Write Data for port A pins PBDR—Port B Data Register H'FFFDA Port B Initial value Read/Write Data for port B pins...
Page 739 ADDRA H/L—A/D Data Register A H/L H'FFFE0, H'FFFE1 Initial value Read/Write ADDRAH ADDRAL A/D conversion data 10-bit data giving an A/D conversion result ADDRB H/L—A/D Data Register B H/L H'FFFE2, H'FFFE3 Initial value Read/Write ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result...
Page 740 ADDRC H/L—A/D Data Register C H/L H'FFFE4, H'FFFE5 Initial value Read/Write ADDRCH ADDRCL A/D conversion data 10-bit data giving an A/D conversion result ADDRD H/L—A/D Data Register D H/L H'FFFE6, H'FFFE7 Initial value Read/Write ADDRDH ADDRDL A/D conversion data 10-bit data giving an A/D conversion result ADCR H/L—A/D Control Register H'FFFE9 TRGE...
Page 741 ADCSR—A/D Control/Status Register H'FFFE8 ADIE ADST SCAN Initial value Read/Write R/(W)* Channel select Clock select Conversion time = Description Group Selection Channel Selection 134 states (maximum) CH1 CH0 Single Mode Scan Mode Conversion time = 70 states (maximum) to AN to AN Scan mode Single mode...
Page 742 Appendix C I/O Port Block Diagrams Port 4 Block Diagram 8-bit bus mode 16-bit bus mode Reset P4 PCR RP4P WP4P Reset Write to external P4 DDR address WP4D Reset P4 DR Read external address WP4P: Write to P4PCR RP4P: Read P4PCR WP4D: Write to P4DDR...
Page 743 Port 6 Block Diagrams Reset P6 DDR Bus controller WP6D WAIT input Reset enable P6 DR Bus controller WAIT WP6D: Write to P6DDR input WP6: Write to port 6 RP6: Read port 6 Figure C.2 (a) Port 6 Block Diagram (Pin P6...
Page 744 Reset controller P6 DDR WP6D Bus release enable Reset P6 DR BREQ input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.2 (b) Port 6 Block Diagram (Pin P6...
Page 745 Reset P6 DDR WP6D Reset P6 DR Bus controller Bus release enable BACK output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.2 (c) Port 6 Block Diagram (Pin P6...
Page 746 Hardware standby φ output enable φ output RP6: Read port 6 Figure C.2 (d) Port 6 Block Diagram (Pin P6...
Page 747 Port 7 Block Diagrams A/D converter Analog input RP7: Read port 7 Input enable n = 0 to 5 Channel select signal Figure C.3 (a) Port 7 Block Diagram (Pins P7 to P7 A/D converter Analog input Input enable Channel select signal D/A converter Output enable Analog output...
Page 748 Port 8 Block Diagrams Reset WP8D Reset Refresh controller Output enable RFSH output Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.4 (a) Port 8 Block Diagram (Pin P8...
Page 749 Reset SSOE Software standby Bus controller WP8D output Reset Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable n = 1 and 2 Figure C.4 (b) Port 8 Block Diagram (Pins P8 , P8...
Page 750 Reset SSOE Software standby Bus controller WP8D output Reset Interrupt controller input A/D converter ADTRG input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable Figure C.4 (c) Port 8 Block Diagram (Pin P8...
Page 751 Reset SSOE Software standby Bus controller WP8D output Reset WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable Figure C.4 (d) Port 8 Block Diagram (Pin P8...
Page 752 Port 9 Block Diagrams Reset P9 DDR WP9D Reset P9 DR Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (a) Port 9 Block Diagram (Pin P9...
Page 753 Reset WP9D Reset Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (b) Port 9 Block Diagram (Pin P9...
Page 754 Reset P9 DDR WP9D Input enable Reset P9 DR Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (c) Port 9 Block Diagram (Pin P9...
Page 755 Reset WP9D Input enable Reset Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (d) Port 9 Block Diagram (Pin P9...
Page 756 Reset P9 DDR WP9D Clock input Reset enable P9 DR Clock output enable Clock output Clock input WP9D: Write to P9DDR Interrupt WP9: Write to port 9 controller RP9: Read port 9 input Figure C.5 (e) Port 9 Block Diagram (Pin P9...
Page 757 Reset P9 DDR WP9D Clock input Reset enable P9 DR Clock output enable Clock output Clock input WP9D: Write to P9DDR Interrupt WP9: Write to port 9 controller RP9: Read port 9 input Figure C.5 (f) Port 9 Block Diagram (Pin P9...
Page 758 Port A Block Diagrams Reset PA DDR WPAD Reset output enable PA DR Next data Output trigger DMA controller Output enable Transfer end output 16-bit timer Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A 8-bit timer n = 0 and 1 Counter...
Page 759 Reset PA DDR WPAD Reset output enable PA DR Next data Output trigger 16-bit timer Output enable Compare match output Input capture Counter clock WPAD: Write to PADDR input WPA: Write to port A RPA: Read port A 8-bit timer n = 2 and 3 Counter clock input...
Page 760 Software standby SSOE Bus released Address output enable Mode 3/4 Reset WPAD Reset TPC output enable Next data Output trigger 16-bit timer Output enable Compare match output Input capture WPAD: Write to PADDR WPA: Write to port A RPA: Read port A SSOE: Software standby output port enable n = 4 to 7...
Page 761 Port B Block Diagrams Software standby SSOE Reset Bus controller WPBD CS5 output Bus released CS output enable Reset TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B SSOE:...
Page 762 Software standby Reset SSOE Bus controller WPBD CS4 output Bus released CS output enable Reset TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output TMO2 TMO3 input DMAC DREQ0 DREQ1 input WPBD: Write to PBDDR WPB: Write to port B RPB:...
Page 763 Reset PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Bus controller CAS output enable CAS output WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.7 (c) Port B Block Diagram (Pin PB...
Page 764 Reset Clock input WPBD enable Reset TPC output enable Next data Output trigger Bus controller CAS output enable CAS output Clock output enable Clock output Clock input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.7 (d) Port B Block Diagram (Pin PB...
Page 765 Reset PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Output enable Serial transmit data Guard time WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.7 (e) Port B Block Diagram (Pin PB...
Page 766 Reset PB DDR WPBD Input enable Reset TPC output enable PB DR Next data Output trigger Serial receive WPBD: Write to PBDDR data WPB: Write to port B RPB: Read port B Figure C.7 (f) Port B Block Diagram (Pin PB...
Page 767 Appendix D Pin States Port States in Each Mode Table D.1 Port States in Each Processing State Hardware Program Port Name Standby Execution Pin Name Mode Reset Mode Software Standby Mode Bus-Released State State RESO — to A 1 to 4 [SSOE = 0] to A [SSOE = 1]...
Page 768 Hardware Program Port Name Standby Execution Pin Name Mode Reset Mode Software Standby Mode Bus-Released State State • When DRAM space • When DRAM space 1 to 4 [RFSHE = 0] is not selected* is not selected* I/O port [RFSHE = 0] [RFSHE = 0] [RFSHE = 1] RFSH...
Page 769 Hardware Program Port Name Standby Execution Pin Name Mode Reset Mode Software Standby Mode Bus-Released State State • RAS • RAS • RAS 1 to 4 output* output* output [SSOE = 0] • Otherwise* • Otherwise [SSOE = 1] [DDR = 0] [DDR = 0] Keep Input port...
Page 770 Hardware Program Port Name Standby Execution Pin Name Mode Reset Mode Software Standby Mode Bus-Released State State 1, 2 Keep Keep I/O port 3, 4 [SSOE = 0] [SSOE = 1] Keep • CS output* • CS output* • CS output , PB 1 to 4 , CS...
Page 771 Hardware Program Port Name Standby Execution Pin Name Mode Reset Mode Software Standby Mode Bus-Released State State • CAS output* • CAS output* • CAS output , PB 1 to 4 UCAS, [SSOE = 0] LCAS • Otherwise* • Otherwise Keep [SSOE = 1] I/O port...
Page 772 14. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is set to 1. 15. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is cleared to 0.
Page 773 Pin States at Reset Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the input state.
Page 774 Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the input state.
Page 775 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
Page 776 HD6413007VF 100-pin QFP (FP-100B) (Low HD6413007VTE HD6413007VTE 100-pin TQFP (TFP-100B) voltage) HD6413007VFP HD6413007VFP 100-pin QFP (FP-100A) H8/3006 5.0 V ± 10% HD6413006F HD6413006F 100-pin QFP (FP-100B) (5 V) HD6413006TE HD6413006TE 100-pin TQFP (TFP-100B) HD6413006FP HD6413006FP 100-pin QFP (FP-100A) 2.7 to 5.5 V...
Page 777 Appendix G Package Dimensions Figure G.1 shows the FP-100B package dimensions of the H8/3006 and H8/3007. Figure G.2 shows the TFP-100B package dimensions. Figure G.3 shows the FP-100A package dimentions. Unit: mm 16.0 ± 0.3 *0.22 ± 0.05 0.08 M 0.20 ±...
Page 778 Unit: mm 16.0 ± 0.2 *0.22 ± 0.05 0.08 0.20 ± 0.04 0° – 8° 0.5 ± 0.1 0.10 Hitachi Code TFP-100B JEDEC — EIAJ Conforms *Dimension including the plating thickness Weight (reference value) 0.5 g Base material dimension Figure G.2 Package Dimensions (TFP-100B)
Page 779 24.8 ± 0.4 Unit: mm *0.32 ± 0.08 0.13 0.30 ± 0.06 0.58 0.83 0° – 10° 1.2 ± 0.2 0.15 Hitachi Code FP-100A JEDEC — EIAJ — *Dimension including the plating thickness Weight (reference value) 1.7 g Base material dimension...
Page 780 Appendix H Comparison of H8/300H Series Product Specifications Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3006 and H8/3007, and H8/3002 H8/3067, H8/3062 H8/3048 Item Series Series H8/3006, H8/3007 H8/3002 Operating Mode 5 16 MB ROM enabled 1 MB ROM...
Page 781 H8/3067, H8/3062 H8/3048 Item Series Series H8/3006, H8/3007 H8/3002 Timer functions 16-bit 8-bit 16-bit 8-bit timers timers timers timers 16 bits × 3 8 bits × 4 16 bits × 5 16 bits × 3 8 bits × 4 16 bits × 5 Number of (16 bits ×...
Page 782 H8/3067, H8/3062 H8/3048 Item Series Series H8/3006, H8/3007 H8/3002 Conversion start External trigger/8-bit External External trigger/8-bit External converter trigger input timer compare match trigger timer compare match trigger φ pin φ/input port multiplexing φ output φ/input port multiplexing φ output...
Page 783 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) Table H.1 Pin Arrangement of Each Product (FP-100B, TFP-100B) On-chip-ROM Products ROMless Products H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006, H8/3007 H8/3002 /TMO /TMO /TMO TIOCA3 TIOCA3 TIOCA3...
Page 784 On-chip-ROM Products ROMless Products H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006, H8/3007 H8/3002...
Page 785 On-chip-ROM Products ROMless Products H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006, H8/3007 H8/3002 /WAIT /WAIT /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /BACK /BACK φ φ φ /φ /φ /φ STBY...
Page 786 On-chip-ROM Products ROMless Products H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006, H8/3007 H8/3002 /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ ADTRG ADTRG ADTRG /TCLKA PA TEND TEND TEND TEND TEND /TCLKA /TCLKA /TCLKA...
Page 787 Publication Date: 1st Edition, December 1997 4th Edition, January 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.

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H8/3007 Hd6413006 Hd6413007