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H8/3006, H8/3007
HD6413006, HD6413007
Hardware Manual
ADE-602-145C
Rev. 4.0
1/29/00
Hitachi, Ltd.

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Summary of Contents for Hitachi H8/3006

  • Page 1 H8/3006, H8/3007 HD6413006, HD6413007 Hardware Manual ADE-602-145C Rev. 4.0 1/29/00 Hitachi, Ltd.
  • Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
  • Page 3 With these features, the H8/3006 and H8/3007 offers easy implementation of compact, high- performance systems. This manual describes the H8/3006 and H8/3007 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.
  • Page 4 List of Items Revised or Added for This Version Page Item Description 1.1 Overview Specification description Table 1-1 Feature Watchdog timer (WDT) amended 2.6.1 Instruction Set Overview Number of instruction types amended Table 2-7 Bit Manipulation Instructions Function description added 2.6.5 Notes on Use of Bit Manipulation Instruction Description added Explanation...
  • Page 5 Page Item Description 8.5.2 Register Configuration Description amended Port 8 Data Register (P8DR) 8.6.2 Register Configuration Description amended Port 9 Data Direction Register (P9DDR) 8.7.2 Register Configuration Description amended Port A Data Direction Register (PADDR) Figure 8.7 Port B Pin Configuration Description added 8.8.2 Register Configuration Description amended...
  • Page 6 Page Item Description B.2 Functions Note deleted P8DDR—Port 8 Data Direction Register B.2 Functions Description amended TSTR—Timer Start Register B.2 Functions Description amended TSNC—Timer Syncro Register B.2 Functions Description amended TMDR—Timer Mode Register B.2 Functions Description amended TISRA—Timer Interrupt Status Register A B.2 Function Description amended TISRB—Timer Interrupt Status Register B...
  • Page 7 Page Item Description B.2 Functions Register names changed, 8TCSR2—Timer Control/Status Register 2 description amended 8TCSR3—Timer Control/Status Register 3 B.2 Functions Register name changed 8TCNT2—Timer Counter 2 8TCNT3—Timer Counter 3 B.2 Functions Description amended P6DR—Port 6 Data Register Figure C.1 Port 4 Block Diagram Figure amended 730 to 732 Figure C.2(a) to Figure C.2(c)
  • Page 8: Table Of Contents

    Contents Section 1 Overview ......................Overview..........................Internal Block Diagram...................... Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ......................1.3.3 Pin Assignments in Each Mode................13 Section 2 CPU ........................17 Overview..........................17 2.1.1 Features ......................... 17 2.1.2 Differences from H8/300 CPU ................18 CPU Operating Modes .......................
  • Page 9 Basic Operational Timing ....................53 2.9.1 Overview....................... 53 2.9.2 On-Chip Memory Access Timing ................ 53 2.9.3 On-Chip Supporting Module Access Timing ............54 2.9.4 Access to External Address Space................ 55 Section 3 MCU Operating Modes ................... 57 Overview..........................57 3.1.1 Operating Mode Selection ..................
  • Page 10 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ..........81 5.2.3 IRQ Status Register (ISR) ..................88 5.2.4 IRQ Enable Register (IER) ................... 89 5.2.5 IRQ Sense Control Register (ISCR) ..............90 Interrupt Sources........................ 91 5.3.1 External Interrupts ....................91 5.3.2 Internal Interrupts....................
  • Page 11 6.4.3 Valid Strobes......................133 6.4.4 Memory Areas ...................... 134 6.4.5 Basic Bus Control Signal Timing ................. 136 6.4.6 Wait Control......................143 DRAM Interface ........................ 145 6.5.1 Overview....................... 145 DRAM Space and RAS Output Pin Settings............145 6.5.2 6.5.3 Address Multiplexing.................... 146 6.5.4 Data Bus........................
  • Page 12 7.2.2 I/O Address Registers (IOAR)................189 7.2.3 Execute Transfer Count Registers (ETCR) ............189 7.2.4 Data Transfer Control Registers (DTCR) ............. 191 Register Descriptions (2) (Full Address Mode) ..............194 7.3.1 Memory Address Registers (MAR)..............194 7.3.2 I/O Address Registers (IOAR)................194 7.3.3 Execute Transfer Count Registers (ETCR) ............
  • Page 13 Port 7..........................251 8.4.1 Overview....................... 251 8.4.2 Register Configuration..................252 Port 8..........................253 8.5.1 Overview....................... 253 8.5.2 Register Configuration..................254 Port 9..........................257 8.6.1 Overview....................... 257 8.6.2 Register Configuration..................258 Port A ..........................261 8.7.1 Overview....................... 261 8.7.2 Register Configuration..................263 Port B ..........................
  • Page 14 9.4.6 Setting Initial Value of 16-Bit Timer Output............330 Interrupts ..........................331 9.5.1 Setting of Status Flags ..................331 9.5.2 Timing of Clearing of Status Flags............... 333 9.5.3 Interrupt Sources and DMA Controller Activation ..........334 Usage Notes ........................335 Section 10 8-Bit Timers ......................
  • Page 15 Section 11 Programmable Timing Pattern Controller (TPC) ........383 11.1 Overview..........................383 11.1.1 Features ......................... 383 11.1.2 Block Diagram...................... 384 11.1.3 Pin Configuration....................385 11.1.4 Register Configuration..................386 11.2 Register Descriptions ......................387 11.2.1 Port A Data Direction Register (PADDR)............387 11.2.2 Port A Data Register (PADR)................
  • Page 16 12.4 Interrupts ..........................423 12.5 Usage Notes ........................423 Section 13 Serial Communication Interface ..............425 13.1 Overview..........................425 13.1.1 Features ......................... 425 13.1.2 Block Diagram...................... 427 13.1.3 Pin Configuration....................428 13.1.4 Register Configuration..................429 13.2 Register Descriptions ......................430 13.2.1 Receive Shift Register (RSR) ................
  • Page 17 14.3.5 Clock ........................502 14.3.6 Transmitting and Receiving Data ................. 504 14.4 Usage Notes ........................512 Section 15 A/D Converter ....................515 15.1 Overview..........................515 15.1.1 Features ......................... 515 15.1.2 Block Diagram...................... 516 15.1.3 Pin Configuration....................517 15.1.4 Register Configuration..................518 15.2 Register Descriptions ......................
  • Page 18 Section 18 Clock Pulse Generator ................... 549 18.1 Overview..........................549 18.1.1 Block Diagram...................... 549 18.2 Oscillator Circuit........................ 550 18.2.1 Connecting a Crystal Resonator................550 18.2.2 External Clock Input ..................... 552 18.3 Duty Adjustment Circuit....................555 18.4 Prescalers ........................... 555 18.5 Frequency Divider......................555 18.5.1 Register Configuration..................
  • Page 19 20.2.2 AC Characteristics ....................582 20.2.3 A/D Conversion Characteristics ................590 20.2.4 D/A Conversion Characteristics ................592 20.3 Operational Timing......................593 20.3.1 Clock Timing ......................593 20.3.2 Control Signal Timing ..................594 20.3.3 Bus Timing ......................596 20.3.4 DRAM Interface Bus Timing ................602 20.3.5 TPC and I/O Port Timing..................
  • Page 20 Appendix H Comparison of H8/300H Series Product Specifications ....767 Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3007 and H8/3006, and H8/3002 ................. 767 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) ..770 xiii...
  • Page 21: Section 1 Overview

    Section 1 Overview Overview The H8/3006 and H8/3007 are a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Hitachi architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed.
  • Page 22 Feature Description Memory H8/3007 • RAM: 4 kbytes H8/3006 • RAM: 2 kbytes • Seven external interrupt pins: NMI, IRQ to IRQ Interrupt • 36 internal interrupts controller • Three selectable interrupt priority levels • Address space can be partitioned into eight areas, with independent bus...
  • Page 23 Feature Description • Three 16-bit timer channels, capable of processing up to six pulse outputs or 16-bit timer, six pulse inputs 3 channels • 16-bit timer counter (channels 0 to 2) • Two multiplexed output compare/input capture pins (channels 0 to 2) •...
  • Page 24 2.7 to 5.5 V HD6413007VF 100-pin QFP (FP-100B) (Low HD6413007VTE 100-pin TQFP (TFP-100B) voltage) HD6413007VFP 100-pin QFP (FP-100A) 5 V ± 10% H8/3006 HD6413006F 100-pin QFP (FP-100B) (5 V) HD6413006TE 100-pin TQFP (TFP-100B) HD6413006FP 100-pin QFP (FP-100A) 2.7 to 5.5 V HD6413006VF...
  • Page 25: Internal Block Diagram

    Internal Block Diagram Figure 1-1 shows an internal block diagram. Data bus Port 4 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL STBY H8/300H CPU RESO Interrupt controller DMA controller (DMAC) φ/P6 BACK/P6 BREQ/P6 WAIT/P6 Watchdog timer ADTRG/CS (WDT) /IRQ /IRQ...
  • Page 26: Pin Description

    Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3006, H8/3007 FP-100B and TFP-100B packages is shown in figure 1-2, and that of the FP-100A package in figure 1-3. /IRQ /RFSH Top view /IRQ (FP-100B, TFP-100B) /IRQ /IRQ /ADTRG...
  • Page 27 /IRQ /RFSH Top view /IRQ (FP-100A) /IRQ /IRQ /ADTRG /TCLKA/TEND /TCLKB/TEND /TIOCA /TCLKC /TIOCB /TCLKD /TIOCA /TIOCB Figure 1-3 Pin Arrangement (FP-100A, Top View)
  • Page 28: Pin Functions

    1.3.2 Pin Functions Table 1-2 summarizes the pin functions. Table 1-2 Pin Functions Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function Power 1, 35, 68 3, 37, 70 Input Power: For connection to the power supply. Connect all V pins to the system power supply.
  • Page 29 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function System Input Reset input: When driven low, this pin resets control the chip RESO Output Reset output: Outputs the reset signal generated by the watchdog timer to external devices STBY Input Standby: When driven low, this pin forces...
  • Page 30 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function RFSH DRAM Output Refresh: Indicates a refresh cycle interface Output Row address strobe RAS: Row address 89, 88, 5, 91, 90, 7, 6 strobe signal for DRAM Output Write enable WE: Write enable signal for DRAM Output Upper column address strobe UCAS: UCAS...
  • Page 31 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function Program- 9 to 2, 11 to 4, Output TPC output 15 to 0: Pulse output mable 100 to 93 2, 1, timing 100 to pattern controller (TPC) Serial 8, 13, 12 10, 15, Output Transmit data (channels 0, 1, 2): SCI data communi-...
  • Page 32 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function I/O ports to P4 26 to 23, 28 to 25, Input/ Port 4: Eight input/output pins. The direction 21 to 18 23 to 20 output of each pin can be selected in the port 4 data direction register (P4DDR).
  • Page 33: 1.3.3 Pin Assignments In Each Mode

    1.3.3 Pin Assignments in Each Mode Table 1-3 lists the pin assignments in each mode. Table 1-3 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 /TMO /TMO /TMO...
  • Page 34 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4...
  • Page 35 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /φ /φ /φ /φ STBY STBY STBY STBY EXTAL EXTAL EXTAL EXTAL XTAL XTAL XTAL XTAL...
  • Page 36 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 /IRQ /RFSH /IRQ /RFSH /IRQ /RFSH /IRQ /RFSH /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ ADTRG ADTRG ADTRG ADTRG /TCLKA/ /TCLKA/ /TCLKA/ /TCLKA/...
  • Page 37: Section 2 Cpu

    Section 2 CPU Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
  • Page 38: Differences From H8/300 Cpu

     16 × 16-bit register-register multiply: 1.1 µs  32 ÷ 16-bit register-register divide: 1.1 µs • Two CPU operating modes  Normal mode (not available in the H8/3006 and H8/3007)  Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
  • Page 39: Cpu Operating Modes

    Maximum 64 kbytes, program Normal mode* and data areas combined CPU operating modes Maximum 16 Mbytes, program Advanced mode and data areas combined Note: * Normal mode is not available in the H8/3006 and H8/3007. Figure 2-1 CPU Operating Modes...
  • Page 40: Address Space

    Address Space Figure 2-2 shows a simple memory map for the H8/3006 and H8/3007. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
  • Page 41: Register Configuration

    Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend Stack pointer...
  • Page 42: General Registers

    2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
  • Page 43: Control Registers

    General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. Free area SP (ER7) Stack area Figure 2-5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register...
  • Page 44: Initial Cpu Register Values

    Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
  • Page 45: Data Formats

    Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
  • Page 46: Memory Data Formats

    General Data Type Register Data Format Word data Word data Longword data Legend ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats 2.5.2 Memory Data Formats Figure 2-8 shows the data formats on memory.
  • Page 47 Data Type Address Data Format 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2-8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
  • Page 48: Instruction Set

    Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP. 2. Not available in the H8/3006 and H8/3007. 3. Bcc is a generic branching instruction.
  • Page 49: Instructions And Addressing Modes

    2.6.2 Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 — Data —...
  • Page 50: Tables Of Instructions Classified By Function

    2.6.3 Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd) Destination operand (EAs)
  • Page 51 Table 2-3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in this LSI.
  • Page 52 Table 2-4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
  • Page 53 Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder Rd ÷...
  • Page 54 Table 2-5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
  • Page 55 Table 2-7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
  • Page 56 Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨...
  • Page 57 Table 2-8 Branching Instructions Instruction Size Function — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
  • Page 58 Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
  • Page 59: 2.6.4 Basic Instruction Formats

    Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
  • Page 60: Notes On Use Of Bit Manipulation Instructions

    Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2-9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions...
  • Page 61 Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Execution of BCLR Instruction ;Clear bit 0 in data direction register BCLR #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output Output Output Output Output Output Input Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR.
  • Page 62: Addressing Modes And Effective Address Calculation

    Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
  • Page 63 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
  • Page 64: Effective Address Calculation

    7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
  • Page 68: Processing States

    Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing states.
  • Page 69: Program Execution State

    2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
  • Page 70 Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2-12 Classification of Exception Sources Bus request End of bus release Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception handling source Bus-released state...
  • Page 71: Exception-Handling Sequences

    2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address.
  • Page 72: Bus-Released State

    2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external bus master.
  • Page 73: Basic Operational Timing

    Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states.
  • Page 74: On-Chip Supporting Module Access Timing

    φ Address bus Address RD HWR LWR High High impedance to D Figure 2-16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the internal I/O register being accessed.
  • Page 75: Access To External Address Space

    φ Address bus Address RD HWR LWR High High impedance to D Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states.
  • Page 76: Section 3 Mcu Operating Modes

    16 Mbytes. The H8/3006 and H8/3007 can be used only in modes 1 to 4. The inputs at the mode pins must select one of these four modes. The inputs at the mode pins must not be changed during operation.
  • Page 77: Register Configration

    3.1.2 Register Configuration The H8/3006 and H8/3007 have a mode control register (MDCR) that indicates the inputs at the mode pins (MD to MD ), and a system control register (SYSCR). Table 3-2 summarizes these registers. Table 3-2 Registers Address*...
  • Page 78: System Control Register (Syscr)

    System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3006 and H8/3007. SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable Enables or disables on-chip RAM Software standby output port enable...
  • Page 79 Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate.
  • Page 80 Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS , AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as bus control signals (CS outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE Description...
  • Page 81: Operating Mode Descriptions

    Operating Mode Descriptions 3.4.1 Mode 1 A maximum 1-Mbyte address space can be accessed. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
  • Page 82: Pin Functions In Each Operating Mode

    0 in bits 7 to 5 of BRCR. Memory Map in Each Operating Mode Figure 3-1, 3-2 show a memory maps of the H8/3006 and H8/3007. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
  • Page 83 Modes 1 and 2 Modes 3 and 4 (1 Mbyte) (16 Mbytes) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'200000 H'3FFFF H'40000 Area 1 Area 2 H'5FFFF H'3FFFFF H'60000 External address Area 3...
  • Page 84 H'FF8000 space H'FFFFF H'FFF71F H'FFF720 H'FFFF00 On-chip RAM* H'FFFF1F H'FFFF20 Internal I/O registers (2) H'FFFFE9 H'FFFFEA External address space H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3-2 H8/3006 Memory Map in Each Operating Mode...
  • Page 85: Section 4 Exception Handling

    Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
  • Page 86: Exception Vector Table

    4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
  • Page 87 H'0028 to H'0029 H'00FC to H'00FF H'007E to H'007F Notes: 1. Lower 16 bits of the address. 2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table. 3. Normal mode is not available in the H8/3006 and H8/3007.
  • Page 88: Reset

    Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high.
  • Page 89 Figure 4-2 Reset Sequence (Modes 1 and 3)
  • Page 90: Interrupts After Reset

    Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
  • Page 91: Interrupts

    Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ), and 36 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication interface (SCI), and A/D converter.
  • Page 92: Stack Status After Exception Handling

    Figure 4-5 Stack after Completion of Exception Handling Notes on Stack Usage When accessing word data or longword data, the H8/3006 and H8/3007 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP: ER7) should always be kept even.
  • Page 93 Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what happens when the SP value is odd. H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP CCR contents lost Legend...
  • Page 94: Section 5 Interrupt Controller

    Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
  • Page 95: Block Diagram

    5.1.2 Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number TEIE Interrupt controller SYSCR Legend ISCR: IRQ sense control register IER: IRQ enable register ISR:...
  • Page 96: Pin Configuration

    5.1.3 Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Abbreviation I/O Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable to IRQ External interrupt request 5 to 0 Input Maskable interrupts, falling edge or level sensing selectable 5.1.4 Register Configuration...
  • Page 97: Register Descriptions

    Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR).
  • Page 98: Interrupt Priority Registers A And B (Ipra, Iprb)

    Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
  • Page 99 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests...
  • Page 100 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
  • Page 101 Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests. Bit 3 IPRA3 Description WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low priority) (Initial value) WDT, DRAM interface, and A/D converter interrupt requests have priority level 1 (high priority) Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests.
  • Page 102 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 IPRB5 — IPRB3 IPRB2 IPRB1 — Initial value Read/Write Reserved bit Priority level B1 Selects the priority level of SCI channel 2 interrupt requests Priority level B2 Selects the priority level of...
  • Page 103 Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 Description 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests.
  • Page 104 Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 Description SCI0 interrupt requests have priority level 0 (low priority) (Initial value) SCI0 interrupt requests have priority level 1 (high priority) Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 Description...
  • Page 105: Irq Status Register (Isr)

    5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ to IRQ interrupt requests. — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) *...
  • Page 106: Irq Enable Register (Ier)

    5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ to IRQ interrupt requests. — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write IRQ to IRQ enable Reserved bits These bits enable or disable IRQ to IRQ interrupts IER is initialized to H'00 by a reset and in hardware standby mode.
  • Page 107: Irq Sense Control Register (Iscr)

    5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ — — IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write IRQ to IRQ sense control Reserved bits These bits select level sensing or falling-edge sensing for IRQ to IRQ interrupts...
  • Page 108: Interrupt Sources

    Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 36 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR.
  • Page 109: Internal Interrupts

    Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
  • Page 110 Table 5-3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Interrupt Source Origin Vector Number Advanced Mode Priority External H'001C to H'001F — High pins H'0030 to H'0033 IPRA7 H'0034 to H0037 IPRA6 H'0038 to H'003B IPRA5 H'003C to H'003F H'0040 to H'0043 IPRA4 H'0044 to H'0047...
  • Page 111 Vector Address* Interrupt Source Origin Vector Number Advanced Mode Priority IMIA2 16-bit timer H'0080 to H'0083 IPRA0 High (compare match/ channel 2 input capture A2) IMIB2 H'0084 to H'0087 (compare match/ input capture B2) OVI2 (overflow 2) H'0088 to H'008B Reserved —...
  • Page 112 Vector Address* Interrupt Source Origin Vector Number Advanced Mode Priority ERI0 H'00D0 to H'00D3 IPRB3 High (receive error 0) channel 0 RXI0 (receive H'00D4 to H'00D7 data full 0) H'00D8 to H'00DB TXI0 (transmit data empty 0) TEI0 H'00DC to H'00DF (transmit end 0) ERI1 H'00E0 to H'00E3...
  • Page 113: Interrupt Operation

    5.4.1 Interrupt Handling Process The H8/3006 and H8/3007 handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5-4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits.
  • Page 114 Program execution state Interrupt requested? Pending Priority level 1? TEI2 TEI2 I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when UE = 1 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
  • Page 115 priority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5-3. • The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted.
  • Page 116 Figure 5-5 shows the transitions among the above states. ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5-5 Interrupt Masking State Transitions (Example)
  • Page 117 Program execution state Interrupt requested? Pending Priority level 1? TEI2 TEI2 I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5-6 Process Up to Interrupt Acceptance when UE = 0...
  • Page 118: Interrupt Sequence

    5.4.2 Interrupt Sequence Figure 5-7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5-7 Interrupt Sequence...
  • Page 119: Interrupt Response Time

    5.4.3 Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip Item Memory...
  • Page 120: Usage Notes

    Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
  • Page 121: Instructions That Inhibit Interrupts

    5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
  • Page 122: Section 6 Bus Controller

    Section 6 Bus Controller Overview The H8/3006 and H8/3007 have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
  • Page 123 • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle •...
  • Page 124: Block Diagram

    6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. to CS ABWCR ASTCR Area Internal address bus CSCR Internal signals decoder Chip select Bus mode control signal control signals Bus control Bus size control signal circuit Access state control signal Wait request signal Wait state...
  • Page 125: Pin Configuration

    6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus Read Output...
  • Page 126: Register Configuration

    6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address* Name Abbreviation Initial Value H'EE020 Bus width control register ABWCR H'FF* H'EE021 Access state control register ASTCR H'FF H'EE022 Wait control register H WCRH H'FF H'EE023 Wait control register L...
  • Page 127: Register Descriptions

    Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Initial value Modes 1 and 3 Read/Write Modes Initial value 2 and 4 Read/Write When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus...
  • Page 128: Access State Control Register (Astcr)

    6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode.
  • Page 129 WCRH Initial value Read/Write Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
  • Page 130 Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of...
  • Page 131 Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 Bit 4 Description Program wait not inserted when external space area 2 is accessed...
  • Page 132: Bus Release Control Register (Brcr)

    6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. A23E A22E A21E A20E — — — BRLE Initial value Modes...
  • Page 133: Bus Control Register (Bcr)

    Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A output from PA . In modes 1 and 2, this bit cannot be modified and PA has its ordinary port functions. Bit 5 A21E Description...
  • Page 134 Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 Description No idle cycle inserted in case of consecutive external read cycles for different areas Idle cycle inserted in case of consecutive external read cycles for different areas...
  • Page 135: Chip Select Control Register (Cscr)

    Bit 3 BRSTS0 Description Max. 4 words in burst access (burst access on match of address bits above A3) (Initial value) Max. 8 words in burst access (burst access on match of address bits above A4) Bit 2—Reserved: Read-only bit, always read as 1. Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units.
  • Page 136: Dram Control Register A (Drcra)

    CS7E CS6E CS5E CS4E — — — — Initial value Read/Write — — — — Chip select 7 to 4 enable Reserved bits These bits enable or disable chip select signal output CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in software standby mode.
  • Page 137 Description Bit 7 Bit 6 Bit 5 DRAS2 DRAS1 DRAS0 Area 5 Area 4 Area 3 Area 2 Normal Normal Normal Normal Normal Normal Normal DRAM space Normal Normal DRAM space DRAM space Normal Normal DRAM space (CS Normal DRAM space DRAM space DRAM space DRAM space...
  • Page 138: Dram Control Register B (Drcrb)

    Bit 2 Description DRAM interface: RAS up mode selected (Initial value) DRAM interface: RAS down mode selected Bit 1—Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby mode. When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a transition is made to software standby mode after the SRFMD bit has been set to 1.
  • Page 139 DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0. Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface.
  • Page 140 Bit 4—Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit. Bit 4 RCYCE Description Refresh cycles disabled (Initial value)
  • Page 141: Refresh Timer Control/Status Register (Rtmcsr)

    6.2.9 Refresh Timer Control/Status Register (RTMCSR) CMIE CKS2 CKS1 CKS0 — — — Initial value Read/Write R(W)* — — — RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests. Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes.
  • Page 142: Refresh Timer Counter (Rtcnt)

    Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Description Count operation halted (Initial value) φ/2 used as counter clock φ/8 used as counter clock φ/32 used as counter clock φ/128 used as counter clock φ/512 used as counter clock φ/2048 used as counter clock φ/4096 used as counter clock Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 1.
  • Page 143: Refresh Time Constant Register (Rtcor)

    6.2.11 Refresh Time Constant Register (RTCOR) Initial value Read/Write RTCOR is an 8-bit readable/writable register that sets the RTCNT compare-match interval. RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1 in RTMCSR, and RTCNT is simultaneously cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode.
  • Page 144: Operation

    Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
  • Page 145 H'000000 Area 0 Area 0 2 Mbytes 2 Mbytes H'1FFFFF H'200000 Area 1 Area 1 2 Mbytes 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes Area 2 H'5FFFFF 8 Mbytes H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5...
  • Page 146: Bus Specifications

    6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller.
  • Page 147: Memory Interfaces

    Chip Select Signals to CS For each of areas 0 to 7, the H8/3006 and H8/3007 can output a chip select signal (CS ) that goes low when the corresponding area is selected. Figure 6.4 shows the output timing of a CSn signal.
  • Page 148 Output of CS to CS : Output of CS to CS is enabled or disabled in the chip select control register (CSCR). A reset leaves pins CS to CS in the input state. To output chip select signals to CS , the corresponding CSCR bits must be set to 1.
  • Page 149: Basic Bus Interface

    Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D...
  • Page 150: Valid Strobes

    In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
  • Page 151: Memory Areas

    Table 6.4 Data Buses Used and Valid Strobes Area Access Read/Write Address Valid Strobe Upper Data Bus Lower Data Bus Size to D to D 8-bit Byte Read — Valid Invalid access area Write — Undetermined data 16-bit Byte Read Even Valid Invalid...
  • Page 152 Area 7: Area 7 includes the on-chip RAM and registers. The space excluding the on-chip RAM and registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space .
  • Page 153: Basic Bus Control Signal Timing

    6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.7 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states data bus (D to D can be inserted.
  • Page 154 8-Bit, Two-State-Access Areas Figure 6.8 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states data bus (D to D cannot be inserted.
  • Page 155 16-Bit, Three-State-Access Areas Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
  • Page 156 Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.10 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address)
  • Page 157 Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D to D Valid Note: n = 7 to 0 Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access)
  • Page 158 16-Bit, Two-State-Access Areas: Figures 6.12 to 6.14 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
  • Page 159 Bus cycle φ Address bus Odd external address in area n to D Read access Invalid to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address)
  • Page 160: Wait Control

    (Word Access) 6.4.6 Wait Control When accessing external space, the H8/3006 and H8/3007 can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin.
  • Page 161 This is useful when inserting four or more T states, or when changing the number of T states for different external devices. The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space. Figure 6.15 shows an example of the timing for insertion of one program wait state in 3-state space.
  • Page 162: Dram Interface

    6.5.1 Overview The H8/3006 and H8/3007 are provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM space accessed via the DRAM interface.
  • Page 163: Address Multiplexing

    6.5.3 Address Multiplexing When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of MXC1 and MXC0 and the address multiplexing method.
  • Page 164: Basic Timing

    Table 6.7 DRAM Interface Pins With DRAM Designated Name Function UCAS Upper column Output Upper column address strobe for DRAM address strobe space access (when CSEL = 0 in DRCRB) LCAS Lower column Output Lower column address strobe for DRAM address strobe space access (when CSEL = 0 in DRCRB) UCAS...
  • Page 165: Precharge State Control

    Figure 6.16 Basic Access Timing (CSEL = 0 in DRCRB) 6.5.7 Precharge State Control In the H8/3006 and H8/3007, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (T ) when DRAM space is accessed. This can be changed to two T states by setting the TPC bit to 1 in DRCRB.
  • Page 166: Wait Control

    φ Column to A High CSn (RAS) PB4 /PB5 (UCAS /LCAS) Read access RD(WE) High to D PB4 /PB5 (UCAS /LCAS) Write access RD(WE) 15 to Note: n = 2 to 5 Figure 6.17 Timing with Two Precharge States (CSEL = 0 in DRCRB) 6.5.8 Wait Control In a DRAM access cycle, wait states can be inserted (1) between the T...
  • Page 167: Byte Access Control And Cas Output Pin

    The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin. φ Column to A High CSn(RAS) PB4 /PB5...
  • Page 168 When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output port. Note that RAS down mode cannot be used when a device other than DRAM is connected to external space and HWR and LWR are used as write strobes.
  • Page 169: Burst Operation

    6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output.
  • Page 170 Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB ABWCR Operating Mode MXC1 MXC0 ABWn Bus Width Compared Row Address Modes 1 and 2 16 bits A19 to A9 (1-Mbyte) 8 bits A19 to A8...
  • Page 171 External space access DRAM access DRAM access φ to A CSn (RAS) PB4/PB5 (UCAS/LCAS) to D Note: n = 2 to 5 Figure 6.21 Example of Operation Timing in RAS Down Mode (CSEL = 0) When RAS down mode is selected, the conditions for an asserted RASn signal to return to the high level are as shown below.
  • Page 172 DRAM access cycle φ RASn (a) Access to DRAM space with a different row address CBR refresh cycle φ RASn (b) CAS-before-RAS refresh cycle DRCRA write cycle φ RASn (c) BE bit or RDM bit cleared to 0 in DRCRA External bus released φ...
  • Page 173 When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval setting must be made so that the maximum DRAM RAS pulse width specification is observed.
  • Page 174: Refresh Control

    6.5.11 Refresh Control The H8/3006 and H8/3007 are provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in DRCRB. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR (compare match).
  • Page 175 φ RTCNT H'00 RTCOR Refresh request signal and CMF bit setting signal Figure 6.25 Compare Match Timing φ Area 2 start address Address bus (RAS) PB4/PB5 (UCAS/LCAS) RD(WE) High RFSH High Figure 6.26 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0) The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T ) state, and two RAS output cycle (T...
  • Page 176 Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. The H8/3006 and H8/3007 have a function that places the DRAM in self-refresh mode when the chip enters software standby mode.
  • Page 177: Examples Of Use

    The following conditions must be observed when the self-refresh function is used: • When burst access is selected, RAS up mode must be selected before executing a SLEEP instruction in order to enter software standby mode. Therefore, if RAS down mode has been selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before executing the SLEEP instruction.
  • Page 178 10-bit row address × 10-bit column address type. Up to four DRAMs can be connected by designating areas 2 to 5 as DRAM space. 2-CAS 16-Mbit DRAM 10-bit row address x 10-bit column address x16-bit organization H8/3006 and H8/3007 CS2 (RAS2) CS3 (RAS3) UCAS PB4 (UCAS)
  • Page 179 DRAM with address space that spans a maximum of four areas. Any unused CS pins (in this example, the CS3 pin) can be used as input/output ports. 2-CAS 16-Mbit DRAM 11-bit row address x 10-bit column address H8/3006 and H8/3007 x8-bit organization CS2 (RAS2) PB4 (UCAS)
  • Page 180 The RFSH pin is used in this case, since both DRAMs must be refreshed simultaneously. However, note that RAS down mode cannot be used in this interconnection example. 2-CAS 4-Mbit DRAM 9-bit row address x 9-bit column address H8/3006 and H8/3007 x16-bit organization CS2 (RAS2) UCAS PB4 (UCAS)
  • Page 181: Usage Notes

    Example of Program Setup Procedure: Figure 6.32 shows an example of the program setup procedure. Set ABWCR Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Set DRCRB Set DRCRA Wait for DRAM stabilization time DRAM can be accessed Figure 6.32 Example of Setup Procedure when Using DRAM Interface 6.5.13 Usage Notes Note the following points when using the DRAM refresh function.
  • Page 182 When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction. Similar contention in a transition to self-refresh mode may prevent dependable strobe waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR. •...
  • Page 183 Oscillation stabilization CPU internal cycle CPU cycle time on exit from software (period in which external standby mode bus can be released) φ Address Figure 6.35 Self-Refresh Clearing...
  • Page 184: Interval Timer

    6.6.1 Operation When DRAM is not connected to the H8/3006 and H8/3007 chip, the refresh timer can be used as an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
  • Page 185 φ RTCNT address Address bus Internal write signal Counter clear signal RTCNT H'00 Figure 6.37 Contention between RTCNT Write and Clear Contention between RTCNT Write and Increment: If an increment pulse occurs in the T state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See Figure 6.38. φ...
  • Page 186 Contention between RTCOR Write and Compare Match: If a compare match occurs in the T state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See Figure 6.39. φ Address bus RTCOR address Internal write signal RTCNT RTCOR RTCOR write data...
  • Page 187 Table 6.10 Internal Clock Switchover and RTCNT Operation CKS2 to CKS0 RTCNT Operation Write Timing switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten High switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten...
  • Page 188 CKS2 to CKS0 RTCNT Operation Write Timing High switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten High High switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted state to a low clock source.
  • Page 189: Interrupt Sources

    6.8.1 Overview With the H8/3006 and H8/3007, external space area 0 can be designated as burst ROM space, and burst ROM space interfacing can be performed. The burst ROM interface enables ROM with burst access capability to be accessed at high speed. Area 0 is designated as burst ROM space by means of the BROME bit in BCR.
  • Page 190: Wait Control

    Full access Burst access φ Address bus Only lower address changes Data bus Read data Read data Read data Figure 6.40 Example of Burst ROM Access Timing 6.8.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface.
  • Page 191: Idle Cycle

    6.9.1 Operation When the H8/3006 and H8/3007 chip accesses external space, it can insert a 1-state idle cycle (T between bus cycles in the following cases: (1) when read accesses between different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when external address space other than DRAM space is accessed immediately after a DRAM space access.
  • Page 192: Operation

    Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ φ Address bus Address bus Data bus Data bus Data collision Long buffer-off time (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.42 Example of Idle Cycle Operation (2) (ICIS0 = 1) External Address Space Access Immediately after DRAM Space Access: If a DRAM space access is followed by a non-DRAM external access when HWR and LWR have been selected as the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted...
  • Page 193 Bus cycle A Bus cycle A (DRAM access cycle) Bus cycle B (DRAM access cycle) Bus cycle B φ φ Address bus Address bus HWR/LWR HWR/LWR (UCAS/LCAS) (UCAS/LCAS) Simultaneous change of HWR/LWR and CSn (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS) External read DRAM space read...
  • Page 194: Pin States In Idle Cycle

    Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ φ Address bus Address bus Simultaneous change of RD and CSn Possibility of mutual overlap (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.45 Example of Idle Cycle Operation (5) 6.9.2 Pin States in Idle Cycle Table 6.11 shows the pin states in an idle cycle.
  • Page 195: Bus Arbiter

    6.10 Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right.
  • Page 196 BREQ signal goes high. While the bus is released to an external bus master, the H8/3006 and H8/3007 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK pin in the low output state.
  • Page 197 CPU cycles External bus released CPU cycles φ High-impedance Address Address bus High-impedance Data bus High-impedance High-impedance High High-impedance HWR, LWR BREQ BACK Minimum 3 cycles Figure 6.46 Example of External Bus Master Operation In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.34).
  • Page 198: Register And Pin Input Timing

    6.11 Register and Pin Input Timing 6.11.1 Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.47 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. φ...
  • Page 199: Breq Pin Input Timing

    BRCR Write Timing: Data written to BRCR to switch between A , or A output and generic input or output takes effect starting from the T state of the BRCR write cycle. Figure 6.49 shows the timing when a pin is changed from generic input to A , or A output.
  • Page 200: Section 7 Dma Controller

    Section 7 DMA Controller Overview The H8/3006 and H8/3007 have an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 19.6, Module Standby Function.
  • Page 201: Block Diagram

    7.1.2 Block Diagram Figure 7.1 shows a DMAC block diagram. Internal address bus Address buffer Internal IMIA0 interrupts IMIA1 Arithmetic-logic unit IMIA2 TXI0 MAR0A RXI0 Channel IOAR0A ETCR0A Channel DREQ Control logic DREQ MAR0B TEND Channel IOAR0B TEND DTCR0A ETCR0B Interrupt DEND0A DTCR0B...
  • Page 202: Functional Overview

    7.1.3 Functional Overview Table 7.1 gives an overview of the DMAC functions. Table 7.1 DMAC Functional Overview Address Reg. Length Destina- Transfer Mode Activation Source tion • Compare match/input Short I/O mode capture A interrupts from 16- address • Transfers one byte or one word bit timer channels mode per request...
  • Page 203: Pin Configuration

    7.1.4 Pin Configuration Table 7.2 lists the DMAC pins. Table 7.2 DMAC Pins Abbrevia- Input/ Channel Name tion Output Function DREQ DMA request 0 Input External request for DMAC channel 0 TEND Transfer end 0 Output Transfer end on DMAC channel 0 DREQ DMA request 1 Input...
  • Page 204 Table 7.3 DMAC Registers Channel Address* Name Abbreviation R/W Initial Value H'FFF20 Memory address register 0AR MAR0AR Undetermined H'FFF21 Memory address register 0AE MAR0AE Undetermined H'FFF22 Memory address register 0AH MAR0AH Undetermined H'FFF23 Memory address register 0AL MAR0AL Undetermined H'FFF26 I/O address register 0A IOAR0A Undetermined...
  • Page 205: Register Descriptions (1) (Short Address Mode)

    Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 7.4. Table 7.4 Selection of Short and Full Address Modes Bit 2...
  • Page 206: I/O Address Registers (Ioar)

    7.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF). Initial value Undetermined Read/Write...
  • Page 207 • Repeat mode Initial value Undetermined Read/Write ETCRH Transfer counter Initial value Undetermined Read/Write ETCRL Initial count In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
  • Page 208: Data Transfer Control Registers (Dtcr)

    7.2.4 Data Transfer Control Registers (DTCR) A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel. DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer enable Data transfer select Enables or disables These bits select the data data transfer...
  • Page 209 Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode. Bit 5 DTID Description...
  • Page 210 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source.
  • Page 211: Register Descriptions (2) (Full Address Mode)

    Register Descriptions (2) (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 7.4. 7.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register.
  • Page 212: Execute Transfer Count Registers (Etcr)

    7.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. • Normal mode ETCRA Initial value Undetermined...
  • Page 213 • Block transfer mode ETCRA Initial value Undetermined Read/Write ETCRAH Block size counter Initial value Undetermined Read/Write ETCRAL Initial block size ETCRB Initial value Undetermined Read/Write Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size.
  • Page 214: Data Transfer Control Registers (Dtcr)

    7.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode.
  • Page 215 Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested.
  • Page 216 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1.
  • Page 217 DTCRB DTME — DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Data transfer master enable Enables or disables data transfer, together with Transfer mode select the DTE bit, and is cleared Selects whether the to 0 by an interrupt block area is the source or destination in block Reserved bit transfer mode...
  • Page 218 Bit 6—Reserved: Although reserved, this bit can be written and read. Bit 5—Destination Address Increment/Decrement (DAID) and, Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer.
  • Page 219 Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B...
  • Page 220: Operation

    Operation 7.4.1 Overview Table 7.5 summarizes the DMAC modes. Table 7.5 DMAC Modes Transfer Mode Activation Notes • Short address I/O mode Compare match/input Up to four channels mode Idle mode capture A interrupt from can operate Repeat mode 16-bit timer channels 0 to 2 independently •...
  • Page 221 Repeat Mode: One byte or word is transferred per request. A designated number of these transfers are executed. When the designated number of transfers are completed, the initial address and counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit address and one 8-bit address are specified.
  • Page 222: I/O Mode

    7.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR).
  • Page 223 Figure 7.2 illustrates how I/O mode operates. Address T Transfer IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCR Address T = L DTID DTSZ Address B = L + (–1) •...
  • Page 224: Idle Mode

    Figure 7.3 shows a sample setup procedure for I/O mode. I/O mode setup Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. Set source and Set the transfer count in ETCR. destination addresses Read DTCR while the DTE bit is cleared to 0.
  • Page 225 Table 7.7 Register Functions in Idle Mode Function Activated by SCI0 Receive- Data-Full Interrupt or A/D Converter Conversion Other Register End Interrupt Activation Initial Setting Operation Destination Source Destination or Held fixed address address source address register register Source Destination Source or Held fixed address...
  • Page 226 The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000.
  • Page 227: Repeat Mode

    7.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode.
  • Page 228 Table 7.8 Register Functions in Repeat Mode Function Activated by SCI0 Receive- Data-Full Interrupt or A/D Converter Conversion Other End Interrupt Register Activation Initial Setting Operation Destination Source Transfer Incremented or address address destination or decremented at register register transfer source each transfer until start address ETCRH reaches...
  • Page 229 As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 7.6 illustrates how repeat mode operates.
  • Page 230 Repeat mode Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. Set the transfer count in both ETCRH and ETCRL. Set source and Read DTCR while the DTE bit is cleared to 0. destination addresses Set the DTCR bits as follows.
  • Page 231: Normal Mode

    7.4.5 Normal Mode In normal mode, the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 7.9 indicates the register functions in I/O mode. Table 7.9 Register Functions in Normal Mode Register...
  • Page 232 Figure 7.8 illustrates how normal mode operates. Address T Transfer Address T Address B Address B Legend = initial setting of MARA = initial setting of MARB = initial setting of ETCRA SAID DTSZ = L + SAIDE • (–1) •...
  • Page 233 Figure 7.9 shows a sample setup procedure for normal mode. Normal mode Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA. Set the DTCRB bits as follows. Set initial source address •...
  • Page 234 7.4.6 Block Transfer Mode In block transfer mode, the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 7.10 indicates the register functions in block transfer mode.
  • Page 235 If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N. Figure 7.10 illustrates how block transfer mode operates.
  • Page 236 When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented.
  • Page 237 Start Start (DTE = DTME = 1) (DTE = DTME = 1) Transfer requested? Transfer requested? Get bus Get bus Read from MARA address Read from MARA address MARA = MARA + 1 MARA = MARA + 1 Write to MARB address Write to MARB address MARB = MARB + 1 ETCRAH = ETCRAH –...
  • Page 238: Block Transfer Mode

    Figure 7.12 shows a sample setup procedure for block transfer mode. Block transfer mode Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) Set source address in both ETCRAH and ETCRAL.
  • Page 239: Dmac Activation

    7.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 7.11. Table 7.11 DMAC Activation Sources Short Address Mode Channels Channels Full Address Mode...
  • Page 240 Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be level- sensitive or edge-sensitive.
  • Page 241: Dmac Bus Cycle

    7.4.8 DMAC Bus Cycle Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (T ), it reads from the source address and writes to the destination address.
  • Page 242 Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. DMAC cycle CPU cycle DMAC cycle...
  • Page 243 Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. CPU cycle DMAC cycle CPU cycle φ Source Destination address address Address Figure 7.15 Burst DMA Bus Timing When the DMAC is activated from a DREQ pin there is a minimum interval of four states from when the transfer is requested until the DMAC starts operating*.
  • Page 244 Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. CPU cycle DMAC cycle cycle DMAC cycle φ DREQ Address Minimum 4 states Next sampling point Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode...
  • Page 245 Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. CPU cycle DMAC cycle CPU cycle φ DREQ Address Minimum 4 states Next sampling point Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode...
  • Page 246 Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. End of 1 block transfer DMAC cycle CPU cycle DMAC cycle φ DREQ Address TEND Next sampling Minimum 4 states Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode...
  • Page 247: Multiple-Channel Operation

    7.4.9 Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 7.12 shows the complete priority order. Table 7.12 Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B...
  • Page 248: External Bus Requests, Dram Interface, And Dmac

    DMAC cycle DMAC cycle DMAC cycle (channel 1) cycle (channel 0A) cycle (channel 1) φ Address Figure 7.19 Timing of Multiple-Channel Operations 7.4.10 External Bus Requests, DRAM Interface, and DMAC During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer of the current byte or word.
  • Page 249: Nmi Interrupts And Dmac

    7.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0.
  • Page 250: Aborting A Dmac Transfer

    7.4.12 Aborting a DMAC Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose.
  • Page 251: Exiting Full Address Mode

    7.4.13 Exiting Full Address Mode Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode. Exiting full address mode Clear the DTE bit to 0 in DTCRA, or wait for the transfer to end and the DTE bit...
  • Page 252: Dmac States In Reset State, Standby Modes, And Sleep Mode

    7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters hardware standby mode or software standby mode, the DMAC is initialized and halts.DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer in sleep mode.
  • Page 253: Interrupts

    Interrupts The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority. Table 7.13 DMAC Interrupts Description Interrupt Short Address Mode Full Address Mode Interrupt Priority DEND0A End of transfer on channel 0A End of transfer on channel 0 High DEND0B End of transfer on channel 0B...
  • Page 254: Usage Notes

    Usage Notes 7.6.1 Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 7.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified as source or destination addresses.
  • Page 255: Note On Activating Dmac By Internal Interrupts

    7.6.5 Note on Activating DMAC by Internal Interrupts When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled.
  • Page 256: Nmi Interrupts And Block Transfer Mode

    When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests.
  • Page 257: Bus Cycle When Transfer Is Aborted

    Table 7.14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode 16-Mbyte Mode H'00000 to H'FFFFF H'000000 to H'FFFFFF (0 to 1048575) (0 to 16777215) IOAR H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1048320 to 1048575) (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode. 7.6.8 Bus Cycle when Transfer is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME...
  • Page 258: Section 8 I/O Ports

    Section 8 I/O Ports Overview The H8/3006 and H8/3007 have 6 input/output ports (ports 4, 6, 8, 9, A, and B) and one input-only port (port 7). Table 8.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 8.1.
  • Page 259 Table 8.1 Port Functions Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 • 8-bit I/O port Port 4 to P4 Data input/output (D to D ) and 8-bit generic input/ to D output • Built-in input 8-bit bus mode: generic input/output16-bit bus pull-up mode: data input/output transistors...
  • Page 260 Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 • 8-bit I/O port Port A /TIOCB Output (TP ) from pro- Address output (A grammable timing • Schmitt inputs pattern controller (TPC), input or output (TIOCB for 16-bit timer and generic input/output /TIOCA TPC output (TP...
  • Page 261: Overview

    Port 4 8.2.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.1. When the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus.
  • Page 262 8.2.2 Register Configuration Table 8.2 summarizes the registers of port 4. Table 8.2 Port 4 Registers Address* Name Abbreviation Initial Value H'EE003 Port 4 data direction register P4DDR H'00 H'FFFD3 Port 4 data register P4DR H'00 H'EE03E Port 4 input pull-up control register P4PCR H'00 Note:...
  • Page 263 Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4. When port 4 functions as an output port, the value of this register is output. When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin level is read.
  • Page 264 Table 8.3 Input Pull-Up Transistor States (Port 4) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 8-bit bus mode On/off On/off 16-bit bus mode Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off. Port 6 8.3.1 Overview...
  • Page 265 8.3.2 Register Configuration Table 8.4 summarizes the registers of port 6. Table 8.4 Port 6 Registers Address* Name Abbreviation Initial Value H'EE005 Port 6 data direction register P6DDR H'80 H'FFFD5 Port 6 data register P6DR H'80 Note: * Lower 20 bits of the address in advanced mode. Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6.
  • Page 266 Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data for port 6. When port 6 functions as an output port, the value of this register is output. Initial value Read/Write Data for port 6 pins Bits storing data for port 1 pins Reserved bit Note: * Determined by pin P6...
  • Page 267 Table 8.5 Port 6 Pin Functions Pin Functions and Selection Method /φ Bit PSTOP in MSTCRH selects the pin function as follows. PSTOP φ output Pin function input /BACK Bit BRLE in BRCR and bit P6 DDR select the pin function as follows. BRLE —...
  • Page 268 Port 7 8.4.1 Overview Port 7 is an 8-bit input-only port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.3 shows the pin configuration of port 7.
  • Page 269: Port 7

    8.4.2 Register Configuration Table 8.6 summarizes the port 7 register. Port 7 is an input-only port, and so has no data direction register. Table 8.6 Port 7 Data Register Address* Name Abbreviation Initial Value H'FFFD6 Port 7 data register P7DR Undetermined Note: Lower 20 bits of the address in advanced mode.
  • Page 270: Overview

    Port 8 8.5.1 Overview Port 8 is a 5-bit input/output port that is also used for CS to CS output, RFSH output, IRQ input, and A/D converter ADTRG input. Figure 8.4 shows the pin configuration of port 8. See table 8.8 for the selection of pin functions. See section 15, A/D Converter, for a description of the A/D converter's ADTRG input pin.
  • Page 271: Register Configuration

    8.5.2 Register Configuration Table 8.7 summarizes the registers of port 8. Table 8.7 Port 8 Registers Initial Value Address* Name Abbreviation Mode 1 to 4 H'EE007 Port 8 data direction P8DDR H'F0 register H'FFFD7 Port 8 data register P8DR H'E0 Note: Lower 20 bits of the address in advanced mode.
  • Page 272 P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore, when port 8 functions as an input/output port, if a transition is made to software standby mode while a P8DDR bit is set to 1, the corresponding pin maintains its output state.
  • Page 273 Table 8.8 Port 8 Pin Functions Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows. Pin function input output /IRQ /ADTRG Bit P8 DDR selects the pin function as follows Pin function input output input ADTRG input /IRQ The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P8...
  • Page 274 Port 9 8.6.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
  • Page 275: Port 9

    8.6.2 Register Configuration Table 8.9 summarizes the registers of port 9. Table 8.9 Port 9 Registers Address* Name Abbreviation Initial Value H'EE008 Port 9 data direction register P9DDR H'C0 H'FFFD8 Port 9 data register P9DR H'C0 Note: Lower 20 bits of the address in advanced mode. Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9.
  • Page 276 Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read.
  • Page 277 Table 8.10 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P9 DDR select the pin function as follows. CKE1 — CKE0 — — —...
  • Page 278: Port A

    Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows. SMIF — — — Pin function input output output output* Note: * Functions as the TxD output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance.
  • Page 279 Port A pins PA /TP /TIOCB /A PA /TP /TIOCA /A PA /TP /TIOCB /A PA /TP /TIOCA /A Port A PA /TP /TIOCB /TCLKD PA /TP /TIOCA /TCLKC PA /TP /TEND /TCLKB PA /TP /TEND /TCLKA Pin functions in modes 1 and 2 PA (input/output)/TP (output)/TIOCB (input/output) PA (input/output)/TP (output)/TIOCA (input/output) PA (input/output)/TP (output)/TIOCB (input/output)
  • Page 280: Register Configuration

    8.7.2 Register Configuration Table 8.11 summarizes the registers of port A. Table 8.11 Port A Registers Initial Value Address* Name Abbreviation Modes 1, 2 Modes 3, 4 H'EE009 Port A data direction PADDR H'00 H'80 register H'FFFD9 Port A data register PADR H'00 H'00...
  • Page 281 Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
  • Page 282 Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit PA DDR select the pin TIOCA function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below —...
  • Page 283 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit PA DDR select the pin TIOCA function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below —...
  • Page 284 Table 8.13 Port A Pin Functions (Modes 3, 4) Pin Functions and Selection Method Always used as A output. TIOCB Pin function output Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in BRCR, and bit PA TIOCA select the pin function as follows.
  • Page 285 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in BRCR, and bit PA TIOCA select the pin function as follows. A23E 16-bit timer channel 1 settings (1) in table below (2) in table below —...
  • Page 286 Table 8.14 Port A Pin Functions (Modes 1 to 4) Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, TIOCB bits CKS2 to CKS0 in TCR3 of the 8-bit timer, bit NDER3 in NDERA, and bit PA DDR select the pin function TCLKD as follows.
  • Page 287 Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, TIOCA bits CKS2 to CKS0 in TCR1 of the 8-bit timer, bit NDER2 in NDERA, and bit PA DDR select the pin function TCLKC as follows.
  • Page 288 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, bits CKS2 to CKS0 in TCR2 of TCLKB/ the 8-bit timer, bit NDER1 in NDERA, and bit PA DDR select the pin function as follows. TEND NDER1 —...
  • Page 289: Port B

    Port B 8.8.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TMIO , TMO , TMIO , TMO ) by the 8-bit timer, CS to CS , DREQ output, input (DREQ...
  • Page 290: Register Configuration

    8.8.2 Register Configuration Table 8.15 summarizes the registers of port B. Table 8.15 Port B Registers Address* Name Abbreviation Initial Value H'EE00A Port B data direction register PBDDR H'00 H'FFFDA Port B data register PBDR H'00 Note: Lower 20 bits of the address in advanced mode. Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B.
  • Page 291 Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read.
  • Page 292 Table 8.16 Port B Pin Functions Pin Functions and Selection Method Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB DDR select the pin function as follows. SMIF — — — NDER15 —...
  • Page 293 Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in TCSR3, bits TMIO CCLR1 and CCLR0 in TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB DDR select the pin DREQ function as follows.
  • Page 294 Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in TCSR1, bits CCLR1 and CCLR0 in TCR1, bit CS6E in CSCR, bit NDER9 in TMIO NDERB, and bit PB DDR select the pin function as follows. DREQ OIS3/2 and OS1/0 All 0 Not all 0 CS6E...
  • Page 295: Section 9 16-Bit Timer

    Section 9 16-Bit Timer Overview The H8/3006 and H8/3007 have built-in 16-bit timer module with three 16-bit counter channels. 9.1.1 Features 16-bit timer features are listed below. • Capability to process up to 6 pulse outputs or 6 pulse inputs •...
  • Page 296 • Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. • High-speed access via internal 16-bit bus The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus. • Any initial timer output value can be set •...
  • Page 297 Table 9.1 16-bit timer Functions Item Channel 0 Channel 1 Channel 2 Internal clocks: φ, φ/2, φ/4, φ/8 Clock sources External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers (output GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 compare/input capture registers) Input/output pins TIOCA , TIOCB...
  • Page 298: Block Diagrams

    9.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer. IMIA0 to IMIA2 TCLKA to TCLKD Clock selector IMIB0 to IMIB2 φ, φ/2, φ/4, φ/8 OVI0 to OVI2 Control logic TIOCA to TIOCA TIOCB to TIOCB TSTR...
  • Page 299 Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 9.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 IMIB0 Comparator OVI0 Module data bus Legend...
  • Page 300 Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2 TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2 IMIB2 Comparator OVI2 Module data bus Legend 16TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) ×...
  • Page 301: Pin Configuration

    9.1.3 Pin Configuration Table 9.2 summarizes the 16-bit timer pins. Table 9.2 16-bit timer Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input...
  • Page 302: Register Configuration

    9.1.4 Register Configuration Table 9.3 summarizes the 16-bit timer registers. Table 9.3 16-bit timer Registers Abbre- Initial Channel Address* Name viation Value Common H'FFF60 Timer start register TSTR H'F8 H'FFF61 Timer synchro register TSNC H'F8 H'FFF62 Timer mode register TMDR H'98 H'FFF63 Timer output level setting register...
  • Page 303 Abbre- Initial Channel Address* Name viation Value H'FFF78 Timer control register 2 16TCR2 H'80 H'FFF79 Timer I/O control register 2 TIOR2 H'88 H'FFF7A Timer counter 2H 16TCNT2H R/W H'00 H'FFF7B Timer counter 2L 16TCNT2L R/W H'00 H'FFF7C General register A2H GRA2H H'FF H'FFF7D...
  • Page 304: Register Descriptions

    Register Descriptions 9.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in channels 0 to 2. — — — — — STR2 STR1 STR0 Initial value Read/Write — — — —...
  • Page 305: Timer Synchro Register (Tsnc)

    9.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1. — — — — — SYNC2 SYNC1 SYNC0 Initial value Read/Write —...
  • Page 306: Timer Mode Register (Tmdr)

    Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously. Bit 0 SYNC0 Description Channel 0’s timer counter (16TCNT0) operates independently (Initial value) 16TCNT0 is preset and cleared independently of other channels Channel 0 operates synchronously 16TCNT0 can be synchronously preset and cleared 9.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2.
  • Page 307 When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction Down-Counting Up-Counting...
  • Page 308: Timer Interrupt Status Register A (Tisra)

    Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode. Bit 1 PWM1 Description Channel 1 operates normally (Initial value) Channel 1 operates in PWM mode When bit PWM1 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
  • Page 309 — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0 Initial value Read/Write — — R/(W)* R/(W)* R/(W)* Input capture/compare match flags A2 to A0 Status flags indicating GRA compare match or input capture Reserved bit Input capture/compare match interrupt enable A2 to A0 These bits enable or disable interrupts by the IMFA flags Reserved bit Note: * Only 0 can be written, to clear the flag.
  • Page 310 Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables the interrupt requested by the IMFA0 flag when IMFA0 is set to 1. Bit 4 IMIEA0 Description IMIA0 interrupt requested by IMFA0 flag is disabled (Initial value) IMIA0 interrupt requested by IMFA0 flag is enabled Bit 3—Reserved: This bit cannot be modified and is always read as 1.
  • Page 311: Timer Interrupt Status Register B (Tisrb)

    Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0 compare match or input capture events. Bit 0 IMFA0 Description [Clearing conditions] (Initial value) • Read IMFA0 when IMFA0 =1, then write 0 in IMFA0. • DMAC activated by IMIA0 interrupt. [Setting conditions] •...
  • Page 312 Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables the interrupt requested by the IMFB2 flag when IMFB2 is set to 1. Bit 6 IMIEB2 Description IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value) IMIB2 interrupt requested by IMFB2 flag is enabled Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 flag when IMFB1 is set to 1.
  • Page 313 Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 Description [Clearing condition] (Initial value) Read IMFB1 when IMFB1 =1, then write 0 in IMFB1. [Setting conditions] • 16TCNT1 = GRB1 when GRB1 functions as an output compare register. •...
  • Page 314: Timer Interrupt Status Register C (Tisrc)

    9.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0 Initial value Read/Write — — R/(W)* R/(W)* R/(W)* Overflow flags 2 to 0...
  • Page 315 Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 flag when OVF0 is set to 1. Bit 4 OVIE0 Description OVI0 interrupt requested by OVF0 flag is disabled (Initial value) OVI0 interrupt requested by OVF0 flag is enabled Bit 3—Reserved: This bit cannot be modified and is always read as 1.
  • Page 316: Timer Counters (16Tcnt)

    9.2.7 Timer Counters (16TCNT) 16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel. Channel Abbreviation Function 16TCNT0 Up-counter 16TCNT1 16TCNT2 Phase counting mode: up/down-counter Other modes: up-counter Initial value Read/Write Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
  • Page 317: General Registers (Gra, Grb)

    9.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each channel. Channel Abbreviation Function GRA0, GRB0 Output compare/input capture register GRA1, GRB1 GRA2, GRB2 Initial value Read/Write A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register.
  • Page 318: Timer Control Registers (16Tcr)

    9.2.9 Timer Control Registers (16TCR) 16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel. Channel Abbreviation Function 16TCR0 CR controls the timer counter. The 16TCRs in all channels are 16TCR1 functionally identical. When phase counting mode is 16TCR2 selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
  • Page 319 Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description 16TCNT is not cleared (Initial value) 16TCNT is cleared by GRA compare match or input capture* 16TCNT is cleared by GRB compare match or input capture* Synchronous clear: 16TCNT is cleared in synchronization with other synchronized timers* Notes: 1.
  • Page 320: Timer I/O Control Register (Tior)

    Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 Function Internal clock: φ (Initial value) Internal clock: φ/2 Internal clock: φ/4 Internal clock: φ/8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input...
  • Page 321 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIORA and TIORC pins.
  • Page 322: Timer Output Level Setting Register C (Tolr)

    Bit 3—Reserved: This bit cannot be modified and is always read as 1. Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 Function GRA is an output No output at compare match (Initial value)
  • Page 323 Bit 5—Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB Bit 5 TOB2 Description TIOCB is 0 (Initial value) TIOCB is 1 Bit 4—Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA Bit 4 TOA2 Description TIOCA...
  • Page 324 Bit 0—Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA Bit 0 TOA0 Description TIOCA is 0 (Initial value) TIOCA is 1...
  • Page 325: Cpu Interface

    CPU Interface 9.3.1 16-Bit Accessible Registers The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time.
  • Page 326 On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 9.6 Access to Timer Counter (CPU Writes to 16TCNTH, Upper Byte) On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 9.7 Access to Timer Counter (CPU Writes to 16TCNTL, Lower Byte) On-chip data bus Module Bus interface...
  • Page 327: 8-Bit Accessible Registers

    On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 9.9 Access to Timer Counter (CPU Reads 16TCNTL, Lower Byte) 9.3.2 8-Bit Accessible Registers The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus.
  • Page 328: Operation

    Operation 9.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare.
  • Page 329 Counter setup Select counter clock Type of counting? Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter Figure 9.12 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal.
  • Page 330 • Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC. After the overflow, the counter continues counting up from H'0000.
  • Page 331 16TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 9.14 Periodic Counter Operation • 16TCNT count timing  Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
  • Page 332  External clock source Bits TPSC2 to TPSC0 in 16TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected.
  • Page 333 Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
  • Page 334 16TCNT value H'FFFF H'0000 Time TIOCB No change No change 1 output No change No change 0 output TIOCA Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0) Figure 9.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared by compare match B.
  • Page 335 • Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
  • Page 336 Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the DDR bit to 0 before making these TIOR settings. Select input-capture input Start counter Set the STR bit to 1 in TSTR to start the timer counter.
  • Page 337 • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
  • Page 338: Synchronization

    9.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
  • Page 339 Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0.
  • Page 340: Pwm Mode

    9.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
  • Page 341 Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to Select counter clock select the desired edge(s) of the...
  • Page 342 Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible.
  • Page 343 Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
  • Page 344: Phase Counting Mode

    9.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2.
  • Page 345 Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase counting mode. Table 9.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
  • Page 346: Setting Initial Value Of 16-Bit Timer Output

    9.4.6 Setting Initial Value of 16-Bit Timer Output Any desired value can be specified for the initial 16-bit timer output value when a timer count operation is started by making a setting in TOLR. Figure 9.32 shows the timing for setting the initial output value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
  • Page 347: Interrupts

    Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR).
  • Page 348 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 9.34 shows the timing. φ Input capture signal 16TCNT Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture...
  • Page 349: Timing Of Clearing Of Status Flags

    φ 16TCNT Overflow signal Figure 9.35 Timing of Setting of OVF 9.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared.
  • Page 350: Interrupt Sources And Dma Controller Activation

    9.5.3 Interrupt Sources and DMA Controller Activation Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1.
  • Page 351: Usage Notes

    Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 9.37.
  • Page 352 Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 9.38 shows the timing in this case. 16TCNT word write cycle φ...
  • Page 353 Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the or T state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The 16TCNT byte that was not written retains its previous value. See figure 9.39, which shows an increment pulse occurring in the T state of a byte write to 16TCNTH.
  • Page 354 Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 9.40. General register write cycle φ...
  • Page 355 Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 9.41. 16TCNT write cycle φ...
  • Page 356 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 9.42. General register read cycle φ GR address Address bus Internal read signal Input capture signal...
  • Page 357 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
  • Page 358 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 9.44. General register write cycle φ...
  • Page 359 Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 1 and 2 are synchronized •...
  • Page 360 16-bit timer Operating Modes Table 9.7 (a)16-bit timer Operating Modes (Channel 0) Register Settings TSNC TMDR TIOR0 TCR0 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC0 = 1 — — PWM mode — — PWM0 = 1 —...
  • Page 361 Table 9.7 (b)16-bit timer Operating Modes (Channel 1) Register Settings TSNC TMDR TIOR1 TCR1 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC1 = 1 — — PWM mode — — PWM1 = 1 — Output compare A —...
  • Page 362 Table 9.7 (c)16-bit timer Operating Modes (Channel 2) Register Settings TSNC TMDR TIOR2 TCR2 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC2 = 1 — PWM mode — PWM2 = 1 — Output compare A —...
  • Page 363: Section 10 8-Bit Timers

    10.1 Overview The H8/3006 and H8/3007 have a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events.
  • Page 364 Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources.
  • Page 365: Block Diagram

    10.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer group 0. External clock Internal clock sources...
  • Page 366: Pin Configuration

    10.1.3 Pin Configuration Table 10.1 summarizes the input/output pins of the 8-bit timer module. Table 10.1 8-Bit Timer Pins Group Channel Name Abbreviation I/O Input/output Timer output Output Compare match output Timer clock input TCLKC Input Counter external clock input Timer input/output TMIO Compare match output/input capture input...
  • Page 367: Register Configuration

    10.1.4 Register Configuration Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers Channel Address*1 Name Abbreviation R/W Initial value H’FFF80 Timer control register 0 8TCR0 H’00 H’FFF82 Timer control/status register 0 8TCSR0 R/(W)* H’00 H’FFF84 Timer constant register A0 TCORA0...
  • Page 368: Register Descriptions

    10.2 Register Descriptions 10.2.1 Timer Counters (8TCNT) 8TCNT0 8TCNT1 Initial value Read/Write 8TCNT2 8TCNT3 Initial value Read/Write The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR).
  • Page 369: Time Constant Registers A (Tcora)

    10.2.2 Time Constant Registers A (TCORA) TCORA0 TCORA1 Initial value Read/Write TCORA2 TCORA3 Initial value Read/Write TCORA0 to TCORA3 are 8-bit readable/writable registers. The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access. The TCORA value is constantly compared with the 8TCNT value.
  • Page 370: Time Constant Registers B (Tcorb)

    10.2.3 Time Constant Registers B (TCORB) TCORB0 TCORB1 Initial value Read/Write TCORB2 TCORB3 Initial value Read/Write TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value.
  • Page 371 For the timing, see section 10.4, Operation. Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt request when the CMFB flag is set to 1 in 8TCSR. Bit 7 CMIEB Description CMIB interrupt requested by CMFB is disabled (Initial value) CMIB interrupt requested by CMFB is enabled Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt...
  • Page 372 Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to 8TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192. The rising edge of the selected internal clock triggers the count.
  • Page 373: Timer Control/Status Registers (8Tcsr)

    10.2.5 Timer Control/Status Registers (8TCSR) 8TCSR0 CMFB CMFA ADTE OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* 8TCSR2 CMFB CMFA — OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* — 8TCSR1, 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
  • Page 374 Bit 6—Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA compare match or input capture. Bit 6 CMFA Description Clearing condition (Initial value) Read CMFA when CMFA = 1, then write 0 in CMFA Setting condition 8TCNT = TCORA Bit 5—Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed (H'FF →...
  • Page 375 Bit 4—Input Capture Enable (ICE) (8TCSR1, 8TCSR3): Selects the function of TCORB. Bit 4 Description TCORB is a compare match register (Initial value) TCORB is an input capture register Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge.
  • Page 376 Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A output level. Bit 1 Bit 0 Description No change when compare match A occurs (Initial value) 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) •...
  • Page 377: Cpu Interface

    10.3 CPU Interface 10.3.1 8-Bit Registers 8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time.
  • Page 378 Internal data bus Module data bus interface 8TCNT0 8TCNT1 Figure 10.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1 Figure 10.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1...
  • Page 379: Operation

    10.4 Operation 10.4.1 8TCNT Count Timing 8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected by setting bits CKS2 to CKS0 in 8TCR. Figure 10.8 shows the count timing.
  • Page 380: Compare Match Timing

    φ External clock input 8TCNT input clock 8TCNT N–1 Figure 10.9 Count Timing for External Clock Input (When Detecting the Both Edges) 10.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
  • Page 381: Input Capture Signal Timing

    φ Compare match signal 8TCNT H'00 Figure 10.11 Timing of Clear by Compare Match Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this operation.
  • Page 382: Timing Of Status Flag Setting

    φ Input capture input Input capture signal 8TCNT TCORB Figure 10.13 Timing of Input Capture Input Signal 10.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in 8TCSR are set to 1 by the compare match signal output when the TCOR and 8TCNT values match.
  • Page 383: Operation With Cascaded Connection

    φ 8TCNT TCORB Input capture signal CMFB Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in this case.
  • Page 384 16-Bit Count Mode • Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ...
  • Page 385: Input Capture Setting

     Setting when Input Capture Occurs • The CMFB flag is set to 1 in 8TCR2 and 8TCR3 when the ICE bit is 1 in 8TCSR3 and input capture occurs. • TMIO pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR2.