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Hitachi HD6473048 Hardware Manual

Single-chip microcomputer

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Hitachi Single-Chip Microcomputer

H8/3048 Series

HD64F3048, HD6473048, HD6433048

Hardware Manual

H8/3048

H8/3047

HD6433047

H8/3045

HD6433045

H8/3044

HD6433044

捷多邦，您值得信赖的PCB打样专家！

ADE-602-073B

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Summary of Contents for Hitachi HD6473048

Page 1 捷多邦，您值得信赖的PCB打样专家！ Hitachi Single-Chip Microcomputer H8/3048 Series H8/3048 HD64F3048, HD6473048, HD6433048 H8/3047 HD6433047 H8/3045 HD6433045 H8/3044 HD6433044 Hardware Manual ADE-602-073B...
Page 2 This manual describes the H8/3048 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual. Notes: 1. ZTAT™ (Zero Turn-Around-time) is a trademark of Hitachi, Ltd. 2. F-ZTAT™ (Flexible ZTAT) is a trademark of Hitachi, Ltd.
Page 3: Table Of Contents
Contents Section 1 Overview ...................... Overview......................... Block Diagram........................ Pin Description ....................... 1.3.1 Pin Arrangement..................... 1.3.2 Pin Assignments in Each Mode..............1.3.3 Pin Functions ....................10 Section 2 ....................... 15 Overview......................... 15 2.1.1 Features......................15 2.1.2 Differences from H8/300 CPU ............... 16 CPU Operating Modes....................
Page 4 Basic Operational Timing....................51 2.9.1 Overview......................51 2.9.2 On-Chip Memory Access Timing..............51 2.9.3 On-Chip Supporting Module Access Timing ..........53 2.9.4 Access to External Address Space..............54 Section 3 MCU Operating Modes ................55 Overview......................... 55 3.1.1 Operating Mode Selection ................55 3.1.2 Register Configuration..................
Page 5 5.1.3 Pin Configuration.................... 83 5.1.4 Register Configuration..................83 Register Descriptions...................... 84 5.2.1 System Control Register (SYSCR)..............84 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ........85 5.2.3 IRQ Status Register (ISR) ................92 5.2.4 IRQ Enable Register (IER) ................93 5.2.5 IRQ Sense Control Register (ISCR) ...............
Page 6 6.3.6 Interconnections with Memory (Example)............. 139 6.3.7 Bus Arbiter Operation..................141 Usage Notes ........................144 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM ........ 144 6.4.2 Register Write Timing ..................144 BREQ Input Timing..................144 6.4.3 6.4.4 Transition to Software Standby Mode ............146 Section 7 Refresh Controller ..................
Page 7 8.3.2 I/O Address Registers (IOAR)................ 196 8.3.3 Execute Transfer Count Registers (ETCR)............. 197 8.3.4 Data Transfer Control Registers (DTCR) ............199 Operation ........................205 8.4.1 Overview......................205 8.4.2 I/O Mode......................207 8.4.3 Idle Mode......................209 8.4.4 Repeat Mode....................212 8.4.5 Normal Mode....................
Page 8 9.5.1 Overview......................255 9.5.2 Register Descriptions..................256 Port 5..........................259 9.6.1 Overview......................259 9.6.2 Register Descriptions..................259 Port 6..........................262 9.7.1 Overview......................262 9.7.2 Register Descriptions..................262 Port 7..........................265 9.8.1 Overview......................265 9.8.2 Register Description ..................266 Port 8..........................267 9.9.1 Overview......................
Page 9 10.2.9 Buffer Registers (BRA, BRB) ................ 321 10.2.10 Timer Control Registers (TCR) ..............322 10.2.11 Timer I/O Control Register (TIOR)..............324 10.2.12 Timer Status Register (TSR)................326 10.2.13 Timer Interrupt Enable Register (TIER)............329 10.3 CPU Interface ......................... 331 10.3.1 16-Bit Accessible Registers ................
Page 10 11.3 Operation ........................... 412 11.3.1 Overview......................412 11.3.2 Output Timing....................413 11.3.3 Normal TPC Output..................414 11.3.4 Non-Overlapping TPC Output................ 416 11.3.5 TPC Output Triggering by Input Capture............418 11.4 Usage Notes ........................419 11.4.1 Operation of TPC Output Pins................ 419 11.4.2 Note on Non-Overlapping Output ..............
Page 11 13.2.6 Serial Control Register (SCR) ................ 447 13.2.7 Serial Status Register (SSR) ................451 13.2.8 Bit Rate Register (BRR) ................. 455 13.3 Operation ........................464 13.3.1 Overview......................464 13.3.2 Operation in Asynchronous Mode..............466 13.3.3 Multiprocessor Communication ..............475 13.3.4 Synchronous Operation ..................
Page 12 15.3 CPU Interface ......................... 532 15.4 Operation ........................533 15.4.1 Single Mode (SCAN = 0) ................533 15.4.2 Scan Mode (SCAN = 1).................. 535 15.4.3 Input Sampling and A/D Conversion Time ............ 537 15.4.4 External Trigger Input Timing................ 538 15.5 Interrupts.........................
Page 13 18.4.1 Flash Memory Operation................569 18.4.2 Mode Programming and Flash Memory Address Space ........ 570 18.4.3 Features......................570 18.4.4 Block Diagram....................572 18.4.5 Input/Output Pins.................... 573 18.4.6 Register Configuration..................573 18.5 Flash Memory Register Descriptions ................574 18.5.1 Flash Memory Control Register ..............574 18.5.2 Erase Block Register 1..................
Page 14 19.5.2 Division Control Register (DIVCR) ............... 639 19.5.3 Usage Notes ....................640 Section 20 Power-Down State ..................641 20.1 Overview......................... 641 20.2 Register Configuration....................643 20.2.1 System Control Register (SYSCR)..............643 20.2.2 Module Standby Control Register (MSTCR) ..........645 20.3 Sleep Mode ........................
Page 15 21.4.1 Bus Timing ..................... 686 21.4.2 Refresh Controller Bus Timing............... 690 21.4.3 Control Signal Timing ..................695 21.4.4 Clock Timing ....................697 21.4.5 TPC and I/O Port Timing................697 21.4.6 ITU Timing ..................... 698 21.4.7 SCI Input/Output Timing................699 21.4.8 DMAC Timing....................
Page 16: Overview
The H8/3048 Series is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Hitachi architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed.
Page 17 Table 1-1 Features Feature Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also usable as + eight 16-bit registers or eight 32-bit registers) High-speed operation (flash memory version) • Maximum clock rate: 16 MHz •...
Page 18 Table 1-1 Features (cont) Feature Description Refresh DRAM refresh controller • Directly connectable to 16-bit-wide DRAM • CAS-before-RAS refresh • Self-refresh mode selectable Pseudo-static RAM refresh • Self-refresh mode selectable Usable as an interval timer DMA controller Short address mode (DMAC) •...
Page 19 Table 1-1 Features (cont) Feature Description A/D converter • Resolution: 10 bits • Eight channels, with selection of single or scan mode • Variable analog conversion voltage range • Sample-and-hold function • A/D conversion can be externally triggered D/A converter •...
Page 20: Block Diagram
1.2 Block Diagram Figure 1-1 shows an internal block diagram. Port 3 Port 4 Address bus P5 /A Data bus (upper) P5 /A P5 /A Data bus (lower) P5 /A EXTAL P2 /A XTAL P2 /A ø H8/300H CPU P2 /A STBY P2 /A P2 /A...
Page 21: Pin Description
1.3 Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3048 Series. TIOCA /TP /PB TIOCB /TP /PB TIOCA /TP /PB P6 /LWR TIOCB /TP /PB P6 /HWR TOCXA /TP /PB P6 /RD TOCXB /TP /PB P6 /AS /DREQ /TP /PB ADTRG/DREQ /TP /PB...
Page 22: Pin Assignments In Each Mode
1.3.2 Pin Assignments in Each Mode Table 1-2 lists the pin assignments in each mode. Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin Name PROM Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 EPROM Flash /TIOCA...
Page 23 Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont) Pin Name PROM Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 EPROM Flash /WAIT /WAIT /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BREQ /BREQ...
Page 24 Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont) Pin Name PROM Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 EPROM Flash /RFSH/IRQ /RFSH/IRQ /RFSH/IRQ /RFSH/IRQ /RFSH/IRQ /RFSH/IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ...
Page 25: Pin Functions
1.3.3 Pin Functions Table 1-3 summarizes the pin functions. Table 1-3 Pin Functions Type Symbol Pin No. Name and Function Power 1, 35, 68 Input Power: For connection to the power supply. Connect all V pins to the system power supply.
Page 26 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function System control RES Input Reset input: When driven low, this pin resets the chip RESO Output Reset output: Outputs a reset signal to external devices (RESO/V Also used as a power supply for on-board programming of the flash memory version.
Page 27 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function RFSH Refresh Output Refresh: Indicates a refresh cycle controller Output Row address strobe RAS: Row address strobe signal for DRAM connected to area 3 Output Column address strobe CAS: Column address strobe signal for DRAM connected to area 3;...
Page 28 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function Programmable TP 9 to 2, Output TPC output 15 to 0: Pulse output timing pattern 100 to 93 controller (TPC) Serial com- 13, 12 Output Transmit data (channels 0 and 1): SCI data munication output interface (SCI)
Page 29 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function I/O ports to P5 56 to 53 Input/ Port 5: Four input/output pins. The direction of output each pin can be selected in the port 5 data direction register (P5DDR). to P6 72 to 69, Input/...
Page 30: Cpu
Section 2 CPU 2.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 31: Differences From H8/300 Cpu
• High-speed operation — All frequently-used instructions execute in two to four states — Maximum clock frequency: 18 MHz/16 MHz (flash memory version) — 8/16/32-bit register-register add/subtract: 111 ns/125 ns (flash memory version) × 8-bit register-register multiply: — 8 778 ns/875 ns (flash memory version) —...
Page 32: Cpu Operating Modes
2.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2-1. The H8/3048 Series can be used only in advanced mode. (Information from this point on will apply to advanced mode unless otherwise stated.) Maximum 64 kbytes, program Normal mode...
Page 33: Address Space
2.3 Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3048 Series has various operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting the full 16 Mbytes. Figure 2-2 shows the address ranges of the H8/3048 Series. For further details see section 3.6, Memory Map in Each Operating Mode.
Page 34: Register Configuration
2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend Stack pointer...
Page 35: General Registers
2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 36: Control Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. Free area SP (ER7) Stack area Figure 2-5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR).
Page 37: Initial Cpu Register Values
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
Page 38: Data Formats
2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 39 General Data Type Register Data Format Word data Word data Longword data Legend ERn: General register General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats (2)
Page 40: Memory Data Formats
2.5.2 Memory Data Formats Figure 2-8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 41: Instruction Set
2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2-1. Table 2-1 Instruction Classification Function Instruction Types Data transfer MOV, PUSH , POP , MOVTPE , MOVFPE Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU Logic operations...
Page 42: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ @ (d:8, (d:16, @@ Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 PC) aa:8 —...
Page 43: Tables Of Instructions Classified By Function
2.6.3 Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd) Destination operand (EAs)
Page 44 Table 2-3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3048 Series.
Page 45 Table 2-4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD, B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 46 Table 2-4 Arithmetic Operation Instructions (cont) Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 47 Table 2-5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 48 Table 2-7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 49 Table 2-7 Bit Manipulation Instructions (cont) Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ [¬ (<bit-No.> of <EAd>)] → C BIOR ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
Page 50 Table 2-8 Branching Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 51 Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 52 Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — repeat @ER5+ → @ER6+, R4L – 1 → R4L until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — repeat @ER5+ → @ER6+, R4 – 1 → R4 until R4 = 0 else next;...
Page 53: Basic Instruction Formats
2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Page 54: Notes On Use Of Bit Manipulation Instructions
2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports.
Page 55 1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Page 56 Table 2-12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 16-Mbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1048320 to 1048575) (16776960 to 16777215) 16 bits (@aa:16) H'00000 to H'07FFF, H'000000 to H'007FFF, H'F8000 to H'FFFFF H'FF8000 to H'FFFFFF (0 to 32767, 1015808 to 1048575) (0 to 32767, 16744448 to 16777215) 24 bits (@aa:24)
Page 57: Effective Address Calculation
Specified by @aa:8 Reserved Branch address Figure 2-10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address.
Page 61: Processing States
2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing states.
Page 62: Program Execution State
2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
Page 63 Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2-12 Classification of Exception Sources End of bus release Bus request Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception Bus-released state Sleep mode...
Page 64: Exception-Handling Sequences
2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is RES signal goes low. Reset exception handling starts after that, when RES entered when the changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address.
Page 65: Bus-Released State
2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the refresh controller, and an external bus master.
Page 66: Basic Operational Timing
2.9 Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states.
Page 67 ø Address bus Address RD HWR LWR High High impedance to D Figure 2-16 Pin States during On-Chip Memory Access...
Page 68: On-Chip Supporting Module Access Timing
2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the register being accessed. Figure 2-17 shows the on-chip supporting module access timing. Figure 2-18 indicates the pin states. Bus cycle T state T state...
Page 69: Access To External Address Space
ø Address bus Address RD HWR LWR High High impedance to D Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states.
Page 70: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3048 Series has seven operating modes (modes 1 to 7) that are selected by the mode pins to MD ) as indicated in table 3-1. The input at these pins determines the size of the address space and the initial bus mode.
Page 71: Register Configuration
Modes 5 and 6 are externally expanded modes that enable access to external memory and peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. Mode 6 supports a maximum address space of 16 Mbytes. Mode 7 is a single-chip mode that operates using the on-chip ROM, RAM, and registers, and makes all I/O ports available.
Page 72: Mode Control Register (Mdcr)
3.2 Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3048 Series. — — — — — MDS2 MDS1 MDS0 Initial value — — — Read/Write — — — — — Reserved bits Reserved bits Mode select 2 to 0...
Page 73: System Control Register (Syscr)
3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3048 Series. SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select Selects the valid edge of the NMI input User bit enable...
Page 74 Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate.
Page 75: Operating Mode Descriptions
3.4 Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A to A , permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
Page 76: Mode 7
3.4.7 Mode 7 This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 7 supports a 1-Mbyte address space. 3.5 Pin Functions in Each Operating Mode The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3-3 indicates their functions in each operating mode.
Page 77 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000 H'40000...
Page 78 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (16-Mbyte expanded mode with (single-chip advanced mode) on-chip ROM enabled) on-chip ROM enabled) H'00000 H'000000 H'00000 Vector area Vector area Vector area H'000FF H'0000FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'007FFF H'07FFF...
Page 79 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000 H'40000...
Page 80 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (16-Mbyte expanded mode with (single-chip advanced mode) on-chip ROM enabled) on-chip ROM enabled) H'00000 H'000000 H'00000 Vector area Vector area Vector area H'000FF H'0000FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'007FFF H'07FFF...
Page 81 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'200000 H'3FFFF H'40000...
Page 82 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (16-Mbyte expanded mode with (single-chip advanced mode) on-chip ROM enabled) on-chip ROM enabled) H'00000 H'000000 H'00000 Vector area Vector area Vector area H'000FF H'0000FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'007FFF H'07FFF...
Page 83 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000 H'40000...
Page 84 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (16-Mbyte expanded mode with (single-chip advanced mode) on-chip ROM enabled) on-chip ROM enabled) H'00000 H'000000 H'00000 Vector area Vector area Vector area H'000FF H'0000FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'007FFF H'07FFF...
Page 85: Exception Handling
Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 86: Exception Vector Table
4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Page 87: Reset
4.2 Reset 4.2.1 Overview RES pin goes low, all processing halts and the A reset is the highest-priority exception. When the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules.
Page 88 Figure 4-2 Reset Sequence (Modes 1 and 3)
Page 89 Internal Vector fetch processing Prefetch of first program instruction ø Address bus High to D (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 90: Interrupts After Reset
Prefetch of Internal first program processing Vector fetch instruction ø Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1), (3) Address of reset vector ((1) = H'000000, (2) = H'000002) (2), (4) Start address (contents of reset vector) Start address First instruction of program Figure 4-4 Reset Sequence (Mode 5, 6 and 7)
Page 91: Interrupts
4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ) and 30 internal sources in the on-chip supporting modules. Figure 4-5 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), refresh controller, 16-bit integrated timer unit (ITU), DMA controller (DMAC), serial communication interface (SCI), and A/D converter.
Page 92: Trap Instruction
4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code.
Page 93: Stack Status After Exception Handling
4.5 Stack Status after Exception Handling Figure 4-6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. → SP-4 SP (ER7) SP-3 SP+1 SP-2 SP+2 SP-1 SP+3 SP (ER7) → Stack area SP+4 Even address Before exception handling After exception handling Pushed on stack...
Page 94: Notes On Stack Usage
4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3048 Series regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @–SP) PUSH.L ERn (or MOV.L ERn, @–SP)
Page 95: Interrupt Controller
Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
Page 96: Block Diagram
5.1.2 Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number ADIE Interrupt controller SYSCR Legend IRQ sense control register ISCR: IER: IRQ enable register ISR:...
Page 97: Pin Configuration
5.1.3 Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Abbreviation Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable External interrupt request 5 to 0 IRQ to IRQ Input Maskable interrupts, falling edge or level sensing selectable 5.1.4 Register Configuration Table 5-2 lists the registers of the interrupt controller.
Page 98: Register Descriptions
5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR).
Page 99: Interrupt Priority Registers A And B (Ipra, Iprb)
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 100 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of ITU channel 2 interrupt requests Priority level A1...
Page 101 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 102 Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT and refresh controller interrupt requests. Bit 3 IPRA3 Description WDT and refresh controller interrupt requests have priority level 0 (Initial value) (low priority) WDT and refresh controller interrupt requests have priority level 1 (high priority) Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests.
Page 103 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 IPRB5 — IPRB3 IPRB2 IPRB1 — Initial value Read/Write Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Priority level B2 Selects the priority level of...
Page 104 Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7 IPRB7 Description ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 3 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Page 105 Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 Description SCI0 interrupt requests have priority level 0 (low priority) (Initial value) SCI0 interrupt requests have priority level 1 (high priority) Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 Description...
Page 106: Irq Status Register (Isr)
5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ to IRQ interrupt requests. — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) *...
Page 107: Irq Enable Register (Ier)
5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ to IRQ interrupt requests. — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write IRQ to IRQ enable Reserved bits These bits enable or disable IRQ to IRQ interrupts IER is initialized to H'00 by a reset and in hardware standby mode.
Page 108: Irq Sense Control Register (Iscr)
5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ — — IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write IRQ to IRQ sense control Reserved bits These bits select level sensing or falling-edge sensing for IRQ to IRQ interrupts...
Page 109: Interrupt Sources
5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 30 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and can be used to exit software standby mode.
Page 110: Internal Interrupts
Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). ø IRQn input pin IRQnF Note: n = 5 to 0 Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Page 111 Table 5-3 Interrupt Sources, Vector Addresses, and Priority Vector Interrupt Source Origin Number Vector Address* Priority External pins H'001C to H'001F — High H'0030 to H'0033 IPRA7 H'0034 to H0037 IPRA6 H'0038 to H'003B IPRA5 H'003C to H'003F H'0040 to H'0043 IPRA4 H'0044 to H'0047 Reserved...
Page 112 Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Vector Interrupt Source Origin Number Vector Address* Priority IMIA2 ITU channel 2 H'0080 to H'0083 IPRA0 High (compare match/ input capture A2) IMIB2 H'0084 to H'0087 (compare match/ input capture B2) OVI2 (overflow 2) H'0088 to H'008B Reserved...
Page 113 Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Vector Interrupt Source Origin Number Vector Address* Priority ERI0 (receive error 0) SCI channel 0 H'00D0 to H'00D3 IPRB3 High RXI0 (receive H'00D4 to H'00D7 data full 0) TXI0 (transmit H'00D8 to H'00DB data empty 0) TEI0 (transmit end 0) H'00DC to H'00DF...
Page 114: Interrupt Operation
5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3048 Series handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 115 Program execution state Interrupt requested? Pending Priority level 1? I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when UE = 1...
Page 116 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 117 Figure 5-5 shows the transitions among the above states. ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5-5 Interrupt Masking State Transitions (Example)
Page 118 Program execution state Interrupt requested? Pending Priority level 1? I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5-6 Process Up to Interrupt Acceptance when UE = 0...
Page 119: Interrupt Sequence
5.4.2 Interrupt Sequence Figure 5-7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5-7 Interrupt Sequence (Mode 2, Two-State Access, Stack in External Memory)
Page 120: Interrupt Response Time
5.4.3 Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip Memory No.
Page 121: Usage Notes
5.5 Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 122: Instructions That Inhibit Interrupts
5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 123 2. IRQaF flag clear and IRQbF flag generation compete (IRQaF flag setting). (The ISR read needed for IRQaF flag clear was at IRQbF = 0 but in the time taken for ISR write, IRQbF = 1 was reached.) In all of the setting conditions 1 to 3 and occurrence conditions 1 and 2 are generated, IRQbF clears in error during ISR write for occurrence condition 2 and interrupt processing is not carried out.
Page 124 MOV.B R0L,@ISR Countermeasure 2 During IRQb interrupt processing, carry out IRQb Fflag clear dummy processing. For example, if b = 1 IRQB MOV.B #HFD,R0L MOV.B R0L,@ISR · · ·...
Page 125: Bus Controller
Section 6 Bus Controller 6.1 Overview The H8/3048 Series has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. A bus arbitration function of the bus controller controls the operation of the DMA controller (DMAC) and refresh controller.
Page 126: Block Diagram
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS to CS ABWCR Internal ASTCR address bus Area WCER decoder Chip select CSCR Internal signals control signals Bus mode control signal Bus control circuit Bus size control signal Access state control signal Wait request signal Wait-state...
Page 127: Input/Output Pins
6.1.3 Input/Output Pins Table 6-1 summarizes the bus controller’s input/output pins. Table 6-1 Bus Controller Pins Name Abbreviation Function Chip select 0 to 7 to CS Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus Read Output...
Page 128: Register Descriptions
6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Mode 1, 3, 5, 6 Initial value Mode 2, 4, 7 Read/Write Bits selecting bus width for each area When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus...
Page 129: Access State Control Register (Astcr)
6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode.
Page 130: Wait Control Register (Wcr)
6.2.3 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. — — — — WMS1 WMS0 Initial value Read/Write — — — —...
Page 131: Wait State Controller Enable Register (Wcer)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit 1 Bit 0 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 6.2.4 Wait State Controller Enable Register (WCER)
Page 132: Bus Release Control Register (Brcr)
6.2.5 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A and enables or disables release of the bus to an external device. A23E A22E A21E — — — —...
Page 133: Chip Select Control Register (Cscr)
Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A address output from PA . In modes other than 3, 4, and 6 this bit cannot be modified and PA has its ordinary input/output functions.
Page 134 Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of the corresponding chip select signal. Bit n CSnE Description Output of chip select signal CS is disabled (Initial value) Output of chip select signal CS is enabled Note: n = 7 to 4 Bits 3 to 0—Reserved: Read-only bits, always read as 1.
Page 135: Operation
6.3 Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6-2 shows a general view of the memory map.
Page 136: Chip Select Signals
Chip select signals (CS to CS ) can be output for areas 0 to 7. The bus specifications for each area can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6-3. Table 6-3 Bus Specifications ABWCR ASTCR WCER Bus Specifications Access ABWn...
Page 137 6.3.2 Chip Select Signals For each of areas 0 to 7, the H8/3048 Series can output a chip select signal (CS to CS ) that goes low to indicate when the area is selected. Figure 6-3 shows the output timing of a CS signal (n = 0 to 7).
Page 138: Data Bus
6.3.3 Data Bus The H8/3048 Series allows either 8-bit access or 16-bit access to be designated for each of areas 0 to 7. An 8-bit-access area uses the upper data bus (D to D ). A 16-bit-access area uses both the upper data bus (D to D ) and lower data bus (D to D...
Page 139: Bus Control Signal Timing
6.3.4 Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit, ) is used to access these areas. The LWR three-state-access area. The upper address bus (D to D pin is always high. Wait states can be inserted. Bus cycle ø...
Page 140 8-Bit, Two-State-Access Areas: Figure 6-5 shows the timing of bus control signals for an 8-bit, ) is used to access these areas. The LWR two-state-access area. The upper address bus (D to D pin is always high. Wait states cannot be inserted. Bus cycle ø...
Page 141 16-Bit, Three-State-Access Areas: Figures 6-6 to 6-8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D to D ) is used to access even addresses and the lower address bus (D to D ) is used to access odd addresses.
Page 142 Bus cycle ø Address bus Odd external address in area n Read to D Invalid access D to D Valid High Write access to D Undetermined data Valid D to D Note: n = 7 to 0 Figure 6-7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address)
Page 143 Bus cycle ø Address bus External address in area n Read to D Valid access D to D Valid Write access to D Valid Valid D to D Note: n = 7 to 0 Figure 6-8 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access)
Page 144 16-Bit, Two-State-Access Areas: Figures 6-9 to 6-11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D to D ) is used to access even addresses and the lower address bus (D to D ) is used to access odd addresses.
Page 145 Bus cycle ø Address bus Odd external address in area n Read to D Invalid access Valid D to D High Write access to D Undetermined data D to D Valid Note: n = 7 to 0 Figure 6-10 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address)
Page 146 Bus cycle ø Address bus External address in area n Read to D Valid access Valid D to D Write access to D Valid D to D Valid Note: n = 7 to 0 Figure 6-11 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access)
Page 147: Wait Modes
6.3.5 Wait Modes Four wait modes can be selected as shown in table 6-5. Table 6-5 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode — — — Disabled No wait states —...
Page 148 Wait Mode in Areas Where Wait-State Controller is Disabled External three-state access areas in which the wait-state controller is disabled (ASTn = 1, WCEn = 0) operate in pin wait mode 0. The other wait modes are unavailable. The settings of bits WMS1 and WMS0 are ignored in these areas.
Page 149 Wait Modes in Areas Where Wait-State Controller is Enabled External three-state access areas in which the wait-state controller is enabled (ASTn = 1, WCEn = 1) can operate in pin wait mode 1, pin auto-wait mode, or programmable wait mode, as selected by bits WMS1 and WMS0.
Page 150 Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T ) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T state, the number of wait states (T ) selected by bits WC1 and WC0 are inserted.
Page 151 Programmable Wait Mode: The number of wait states (T ) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6-15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø...
Page 152 Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings. Figure 6-16 shows an example of wait mode settings.
Page 153: Interconnections With Memory (Example)
6.3.6 Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and an 8- or 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices.
Page 154 EPROM to A to A to I/O H8/3048 Series I/O to I/O SRAM1 (even addresses) to A to A I/O to I/O WAIT SRAM2 (odd addresses) to A to A to A I/O to I/O to D SRAM3 D to D to A to A I/O to I/O...
Page 155: Bus Arbiter Operation
6.3.7 Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right.
Page 156 DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus.
Page 157 Figure 6-19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until the bus is released. CPU cycles External bus released CPU cycles...
Page 158: Usage Notes
6.4 Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. 6.4.2 Register Write Timing ABWCR, ASTCR, and WCER Write Timing: Data written to ABWCR, ASTCR, or WCER takes effect starting from the next bus cycle.
Page 159 DDR Write Timing: Data written to a data direction register (DDR) to change a CS pin from output to generic input, or vice versa, takes effect starting from the T state of the DDR write cycle. Figure 6-21 shows the timing when the CS pin is changed from generic input to CS output.
Page 160: Breq Input Timing
BREQ Input Timing 6.4.3 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes low, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
Page 161: Refresh Controller
Section 7 Refresh Controller 7.1 Overview The H8/3048 Series has an on-chip refresh controller that enables direct connection of 16-bit-wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space. A maximum 128 kbytes can be connected in modes 1, 2 and 5 (1-Mbyte modes).
Page 162: Block Diagram
Features as an Interval Timer • Refresh timer counter (RTCNT) can be used as an 8-bit up-counter • Selection of seven counter clock sources: ø/2, ø/8, ø/32, ø/128, ø/512, ø/2048, ø/4096 • Interrupts can be generated by compare match between RTCNT and the refresh time constant register (RTCOR) 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the refresh controller.
Page 163: Input/Output Pins
7.1.3 Input/Output Pins Table 7-1 summarizes the refresh controller’s input/output pins. Table 7-1 Refresh Controller Pins Signal Name Abbr. Function RFSH RFSH Refresh Output Goes low during refresh cycles; used to refresh DRAM and PSRAM UW/UCAS Connects to the UW pin of 2WE Upper write/upper column Output DRAM or UCAS pin of 2CAS DRAM...
Page 164: Register Descriptions
7.2 Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. SRFMD PSRAME DRAME CAS/WE M9/M8 RFSHE — RCYCE Initial value Read/Write — Refresh cycle enable Enables or disables insertion of refresh cycles...
Page 165 Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when the H8/3048 Series enters software standby mode.
Page 166 Bit 4—Strobe Mode Select (CAS/WE): Selects 2CAS or 2WE mode. The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set to 1. Bit 4 CAS/WE Description 2WE mode...
Page 167: Refresh Timer Control/Status Register (Rtmcsr)
7.2.2 Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. CMIE CKS2 CKS1 CKS0 —...
Page 168 Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit 6 CMIE Description The CMI interrupt requested by CMF is disabled...
Page 169: Refresh Timer Counter (Rtcnt)
7.2.3 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. Initial value Read/Write RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag is set to 1 and RTCNT is cleared to H'00.
Page 170: Operation
7.3 Operation 7.3.1 Overview One of three functions can be selected for the H8/3048 Series refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table 7-3 summarizes the register settings when these three functions are used. Table 7-3 Refresh Controller Settings Usage Register Settings...
Page 171: Dram Refresh Control
Interval Timer: When PSRAME = 0 and DRAME = 0, the refresh controller operates as an interval timer. After setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1. CMI interrupts will be requested at compare match intervals determined by RTCOR and bits CKS2 to CKS0 in RTMCSR.
Page 172 Table 7-4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles Area 3 Settings Read/Write Cycle by CPU or DMAC Refresh Cycle 2-state-access area • 3 states • 3 states (AST3 = 0) • Wait states cannot be inserted • Wait states cannot be inserted 3-state-access area •...
Page 173 Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in RFSHCR, as described in table 7-5. Figure 7-4 shows the address output timing. Address output is multiplexed only in area 3. Table 7-5 Address Multiplexing Address Pins to A Address signals during row to A...
Page 174 2CAS and 2WE Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bit- wide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM pins correspond to H8/3048 Series pins as shown in table 7-6. Table 7-6 DRAM Pins and H8/3048 Series Pins DRAM Pin H8/3048 Series Pin...
Page 175 Read cycle Write cycle Refresh cycle ø Address Column Column Area 3 top address UCAS LCAS RFSH Note: 16-bit access Figure 7-5 DRAM Control Signal Output Timing (2) (2CAS Mode) Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master >...
Page 176 Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the CAS and RAS outputs go low in that order so that the DRAM self-refresh function can be used. On exit from software standby mode, the CAS and RAS outputs both go high.
Page 177 Software Oscillator standby mode settling time ø High-impedance Address CS (RAS) RD (CAS) HWR (UW) High LWR (LW) High RFSH a. 2 mode (SRFMD = 1) Software Oscillator standby mode settling time ø High-impedance Address CS (RAS) (UCAS) (LCAS) RD (WE) RFSH b.
Page 178 Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby mode.
Page 179 Set area 3 for 16-bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-8 Setup Procedure for 2WE 1-Mbit DRAM (1-Mbyte Mode)
Page 180 Example 2: Connection to 2WE 4-Mbit DRAM (16-Mbyte Mode): Figure 7-9 shows typical interconnections to a single 2WE 4-Mbit DRAM, and the corresponding address map. Figure 7-10 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 10-bit row addresses and 8-bit column addresses.
Page 181 Set area 3 for 16-bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-10 Setup Procedure for 2WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit Column Address (16-Mbyte Mode)
Page 182 Example 3: Connection to 2CAS 4-Mbit DRAM (16-Mbyte Mode): Figure 7-11 shows typical interconnections to a single 2CAS 4-Mbit DRAM, and the corresponding address map. Figure 7-12 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 9-bit row addresses and 9-bit column addresses.
Page 183 Set area 3 for 16-bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'3B in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-12 Setup Procedure for 2CAS 4-Mbit DRAM with 9-Bit Row Address and 9-Bit Column Address (16-Mbyte Mode)
Page 184 Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7-13 shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits and A Figure 7-14 shows a setup procedure to be followed by a program for this example.
Page 185 Set area 3 for 16-bit access Set P8 DDR to 1 for CS output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'3F in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-14 Setup Procedure for Multiple 2CAS 4-Mbit DRAM Chips with 9-Bit Row Address and 9-Bit Column Address (16-Mbyte Mode)
Page 186: Pseudo-Static Ram Refresh Control
7.3.3 Pseudo-Static RAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh cycles are the same as for DRAM (see table 7-4).
Page 187 Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master > refresh controller > DMA controller > CPU (Low) For details see section 6.3.7, Bus Arbiter Operation. Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can insert wait states into bus cycles and refresh cycles.
Page 188 Oscillator Software standby mode settling time ø High-impedance Address High High-impedance High-impedance High-impedance RFSH Figure 7-16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0) Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode.
Page 189 Example: Pseudo-static RAM may have separate OE and RFSH pins, or these may be combined into a single OE/RFSH pin. Figure 7-17 shows an example of a circuit for generating an OE/RFSH signal. Check the device characteristics carefully, and design a circuit that fits them. Figure 7-18 shows a setup procedure to be followed by a program.
Page 190 Set P8 DDR to 1 for CS output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'47 in RFSHCR Wait for PSRAM to be initialized PSRAM can be accessed Figure 7-18 Setup Procedure for Pseudo-Static RAM...
Page 191: Interval Timing
7.3.4 Interval Timing To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1. Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag in RTCSR is set to 1 by a compare match signal output when the RTCOR and RTCNT values match.
Page 192 Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the state of an RTCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 7-20. RTCNT write cycle by CPU ø...
Page 193 Contention between RTCNT Write and Increment: If an increment pulse occurs in the T state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7-21. RTCNT write cycle by CPU ø RTCNT address Address bus Internal write signal RTCNT...
Page 194 Contention between RTCOR Write and Compare Match: If a compare match occurs in the T state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 7-22. RTCOR write cycle by CPU ø RTCNT address Address bus Internal...
Page 195 Table 7-9 Internal Clock Switchover and RTCNT Operation CKS2 to CKS0 Write Timing RTCNT Operation Low → low switchover Old clock source New clock source RTCNT clock RTCNT N + 1 CKS bits rewritten Low → high switchover Old clock source New clock source...
Page 196 Table 7-9 Internal Clock Switchover and RTCNT Operation (cont) CKS2 to CKS0 Write Timing RTCNT Operation High → low switchover Old clock source New clock source RTCNT clock RTCNT N + 1 N + 2 CKS bits rewritten High → high switchover Old clock source New clock...
Page 197: Interrupt Source
7.4 Interrupt Source Compare match interrupts (CMI) can be generated when the refresh controller is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of RTMCSR. 7.5 Usage Notes When using the DRAM or pseudo-static RAM refresh function, note the following points: •...
Page 198 Bus-released state Refresh cycle CPU cycle Refresh cycle ø RFSH Refresh request BACK Figure 7-24 Refresh Cycles when Bus is Released • If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the bus-released state.
Page 199: Dma Controller
Section 8 DMA Controller 8.1 Overview The H8/3048 Series has an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 20.6, Module Standby Function.
Page 200: Block Diagram
8.1.2 Block Diagram Figure 8-1 shows a DMAC block diagram. Internal address bus Address buffer Internal IMIA0 interrupts IMIA1 Arithmetic-logic unit IMIA2 IMIA3 TXI0 MAR0A RXI0 Channel IOAR0A ETCR0A Channel DREQ0 Control logic DREQ1 MAR0B TEND0 Channel IOAR0B TEND1 DTCR0A ETCR0B Interrupt DEND0A...
Page 201: Functional Overview
8.1.3 Functional Overview Table 8-1 gives an overview of the DMAC functions. Table 8-1 DMAC Functional Overview Address Reg. Length Destina- Transfer Mode Activation Source tion Short I/O mode • Compare match/input 24 address • Transfers one byte or one word capture A interrupts mode per request...
Page 202: Input/Output Pins
8.1.4 Input/Output Pins Table 8-2 lists the DMAC pins. Table 8-2 DMAC Pins Abbrevia- Input/ Channel Name tion Output Function DMA request 0 DREQ Input External request for DMAC channel 0 Transfer end 0 TEND Output Transfer end on DMAC channel 0 DMA request 1 DREQ Input...
Page 203 Table 8-3 DMAC Registers Channel Address* Name Abbreviation Initial Value H'FF20 Memory address register 0AR MAR0AR Undetermined H'FF21 Memory address register 0AE MAR0AE Undetermined H'FF22 Memory address register 0AH MAR0AH Undetermined H'FF23 Memory address register 0AL MAR0AL Undetermined H'FF26 I/O address register 0A IOAR0A Undetermined H'FF24...
Page 204: Register Descriptions (Short Address Mode)
8.2 Register Descriptions (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 8-4. Table 8-4 Selection of Short and Full Address Modes Bit 2 Bit 1...
Page 205: I/O Address Registers (Ioar)
8.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF). Initial value Undetermined Read/Write...
Page 206 • Repeat mode Initial value Undetermined Read/Write ETCRH Transfer counter Initial value Undetermined Read/Write ETCRL Initial count In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
Page 207: Data Transfer Control Registers (Dtcr)
8.2.4 Data Transfer Control Registers (DTCR) A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel. DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer enable Data transfer select Enables or disables These bits select the data data transfer...
Page 208 Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode. Bit 5 DTID Description...
Page 209 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source.
Page 210: Register Descriptions (Full Address Mode)
8.3 Register Descriptions (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 8-4. 8.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register.
Page 211: Execute Transfer Count Registers (Etcr)
8.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. • Normal mode ETCRA Undetermined...
Page 212 • Block transfer mode ETCRA Initial value Undetermined Read/Write ETCRAH Block size counter Initial value Undetermined Read/Write ETCRAL Initial block size ETCRB Undetermined Initial value Read/Write Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size.
Page 213: Data Transfer Control Registers (Dtcr)
8.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode.
Page 214 Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested.
Page 215 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1.
Page 216 DTCRB DTME — DAID DAIDE DTS2B DTS0B DTS1B Initial value Read/Write Data transfer master enable Enables or disables data transfer, together with Transfer mode select the DTE bit, and is cleared Selects whether the to 0 by an interrupt block area is the source or destination in block Reserved bit transfer mode...
Page 217 Bit 6—Reserved: Although reserved, this bit can be written and read. Bit 5—Destination Address Increment/Decrement (DAID) and Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer. Bit 5 Bit 4 DAID...
Page 218 Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B...
Page 219: Operation
8.4 Operation 8.4.1 Overview Table 8-5 summarizes the DMAC modes. Table 8-5 DMAC Modes Transfer Mode Activation Notes I/O mode • Up to four channels Short address Compare match/input can operate mode capture A interrupt from Idle mode independently ITU channels 0 to 3 Repeat mode •...
Page 220 Normal Mode • Auto-request The DMAC is activated by register setup alone, and continues executing transfers until the designated number of transfers have been completed. A CPU interrupt can be requested at completion of the transfers. Both addresses are 24-bit addresses. —...
Page 221: I/O Mode
8.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR).
Page 222 Address T Transfer IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCR Address T = L DTID DTSZ Address B = L + (–1) • (2 •...
Page 223: Idle Mode
Figure 8-3 shows a sample setup procedure for I/O mode. I/O mode setup Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. Set source and Set the transfer count in ETCR. destination addresses Read DTCR while the DTE bit is cleared to 0.
Page 224 Table 8-7 Register Functions in Idle Mode Function Activated by SCI 0 Receive- Data-Full Other Register Interrupt Activation Initial Setting Operation Destination Source Destination or Held fixed address address source address register register Source Destination Source or Held fixed address address destination All 1s...
Page 225 The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000.
Page 226: Repeat Mode
8.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode.
Page 227 In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID bits in DTCR.
Page 228 The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer count is 255, obtained by setting both ETCRH and ETCRL to H'FF. Transfers can be requested (activated) by compare match/input capture A interrupts from ITU channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and external request signals.
Page 229: Normal Mode
8.4.5 Normal Mode In normal mode the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 8-9 indicates the register functions in I/O mode. Table 8-9 Register Functions in Normal Mode Register Function...
Page 230 Transfer Address T Address T Address B Address B Legend = initial setting of MARA = initial setting of MARB = initial setting of ETCRA SAID DTSZ = L + SAIDE • (–1) • (2 • N – 1) DAID DTSZ = L + DAIDE •...
Page 231 Figure 8-9 shows a sample setup procedure for normal mode. Normal mode Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA. Set the DTCRB bits as follows. Set initial source address •...
Page 232: Block Transfer Mode
8.4.6 Block Transfer Mode In block transfer mode the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 8-10 indicates the register functions in block transfer mode.
Page 233 If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N. Figure 8-10 illustrates how block transfer mode operates.
Page 234 When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented.
Page 235 Start Start (DTE = DTME = 1) (DTE = DTME = 1) Transfer requested? Transfer requested? Get bus Get bus Read from MARA address Read from MARA address MARA = MARA + 1 MARA = MARA + 1 Write to MARB address Write to MARB address MARB = MARB + 1 ETCRAH = ETCRAH –...
Page 236 Figure 8-12 shows a sample setup procedure for block transfer mode. Block transfer mode Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) Set source address in both ETCRAH and ETCRAL.
Page 237: Dmac Activation
8.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 8-11. Table 8-11 DMAC Activation Sources Short Address Mode Full Address Mode Channels Channels...
Page 238 Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be level- sensitive or edge-sensitive.
Page 239: Dmac Bus Cycle
8.4.8 DMAC Bus Cycle Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (T ), it reads from the source address and writes to the destination address.
Page 240 Figure 8-14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. DMAC cycle CPU cycle DMAC cycle...
Page 241 Figure 8-15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. CPU cycle DMAC cycle CPU cyc ø Source Destination address address Address Figure 8-15 Burst DMA Bus Timing When the DMAC is activated from a DREQ pin there is a minimum interval of four states from when the transfer is requested until the DMAC starts operating.
Page 242 Figure 8-16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. CPU cycle DMAC cycle cycle DMAC cycle ø DREQ Address Minimum 4 states Next sampling point Figure 8-16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode...
Page 243 Figure 8-17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. CPU cycle DMAC cycle CPU cycle ø DREQ Address Minimum 4 states Next sampling point Figure 8-17 Timing of DMAC Activation by Low DREQ Level in Normal Mode...
Page 244 Figure 8-18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. End of 1 block transfer DMAC cycle CPU cycle DMAC cycle ø DREQ Address TEND Next sampling Minimum 4 states Figure 8-18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode...
Page 245: Multiple-Channel Operation
8.4.9 DMAC Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 8-12 shows the complete priority order. Table 8-12 Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High...
Page 246: External Bus Requests, Refresh Controller, And Dmac
DMAC cycle DMAC cycle DMAC cycle (channel 1) cycle (channel 0A) cycle (channel 1) ø Address Figure 8-19 Timing of Multiple-Channel Operations 8.4.10 External Bus Requests, Refresh Controller, and DMAC During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or by the refresh controller, the DMAC releases the bus after completing the transfer of the current byte or word.
Page 247: Nmi Interrupts And Dmac
8.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0.
Page 248: Aborting A Dma Transfer
8.4.12 Aborting a DMA Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose.
Page 249: Exiting Full Address Mode
8.4.13 Exiting Full Address Mode Figure 8-23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode. Exiting full address mode Clear the DTE bit to 0 in DTCRA, or wait for the transfer to end and the DTE bit...
Page 250: Dmac States In Reset State, Standby Modes, And Sleep Mode
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters hardware or software standby mode, the DMAC is initialized and halts. DMAC operations continue in sleep mode. Figure 8-24 shows the timing of a cycle-steal transfer in sleep mode.
Page 251: Interrupts
8.5 Interrupts The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority. Table 8-13 DMAC Interrupts Description Interrupt Short Address Mode Full Address Mode Interrupt Priority DEND0A End of transfer on channel 0A End of transfer on channel 0 High DEND0B End of transfer on channel 0B...
Page 252: Usage Notes
8.6 Usage Notes 8.6.1 Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 8.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle.
Page 253: Note On Activating Dmac By Internal Interrupts
8.6.5 Note on Activating DMAC by Internal Interrupts When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled.
Page 254: Nmi Interrupts And Block Transfer Mode
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one ITU interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests.
Page 255: Bus Cycle When Transfer Is Aborted
Table 8-14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode 16-Mbyte Mode H'00000 to H'FFFFF H'000000 to H'FFFFFF (0 to 1048575) (0 to 16777215) IOAR H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1048320 to 1048575) (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode. 8.6.8 Bus Cycle when Transfer is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead...
Page 256: I/O Ports
Section 9 I/O Ports 9.1 Overview The H8/3048 Series has 10 input/output ports (ports 1, 2, 3, 4, 5, 6, 8, 9, A, and B) and one input port (port 7). Table 9-1 summarizes the port functions. The pins in each port are multiplexed as shown in table 9-1.
Page 257 Table 9-1 Port Functions Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O port to P1 Address output pins (A to A Address output (A Generic • Can drive LEDs to A ) and generic input input/...
Page 258 Table 9-1 Port Functions (cont) Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 9 • 6-bit I/O port /SCK /IRQ , Input and output (SCK , SCK , RxD , RxD , TxD , TxD ) for serial...
Page 259 Table 9-1 Port Functions (cont) Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port B • 8-bit I/O port TPC output (TP to TP ), ITU input and output (TOCXB , TOCXA •...
Page 260 9.2.2 Register Descriptions Table 9-2 summarizes the registers of port 1. Table 9-2 Port 1 Registers Initial Value Address* Name Abbreviation Modes 1 to 4 Modes 5 to 7 H'FFC0 Port 1 data direction register P1DDR H'FF H'00 H'FFC2 Port 1 data register P1DR H'00 H'00...
Page 261 In modes 5 to 7, P1DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P1DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode.
Page 262 9.3 Port 2 9.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 9-2. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus output pins (A to A ).
Page 263 9.3.2 Register Descriptions Table 9-3 summarizes the registers of port 2. Table 9-3 Port 2 Registers Initial Value Address* Name Abbreviation Modes 1 to 4 Modes 5 to 7 H'FFC1 Port 2 data direction register P2DDR H'FF H'00 H'FFC3 Port 2 data register P2DR H'00 H'00...
Page 264 In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P2DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode.
Page 265 Table 9-4 summarizes the states of the input pull-up transistors. Table 9-4 Input Pull-Up MOS States (Port 2) Mode Reset Hardware Standby Mode Software Standby Mode Other Modes On/off On/off Legend Off: The input pull-up MOS is always off. On/off: The input pull-up MOS is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off.
Page 266 9.4 Port 3 9.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 9-3. Port 3 is a data bus in modes 1 to 6 (expanded modes) and a generic input/output port in mode 7 (single-chip mode).
Page 267 Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value Read/Write Port 3 data direction 7 to 0...
Page 268 9.5 Port 4 9.5.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 9-4. The pin functions differ according to the operating mode. In modes 1 to 6 (expanded modes), when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port.
Page 269: Register Descriptions
9.5.2 Register Descriptions Table 9-6 summarizes the registers of port 4. Table 9-6 Port 4 Registers Address* Name Abbreviation Initial Value H'FFC5 Port 4 data direction register P4DDR H'00 H'FFC7 Port 4 data register P4DR H'00 H'FFDA Port 4 input pull-up MOS P4PCR H'00 control register...
Page 270 ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a generic input/output port, if a P4DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for pins P4 to P4 .
Page 271 Table 9-7 summarizes the states of the input pull-ups MOS in the 8-bit and 16-bit bus modes. Table 9-7 Input Pull-Up MOS Transistor States (Port 4) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 1 to 6 8-bit bus mode On/off On/off 16-bit bus mode...
Page 272 9.6 Port 5 9.6.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 9-5. The pin functions differ depending on the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A to A ).
Page 273 Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. — P5 DDR P5 DDR P5 DDR — — — P5 DDR Initial value Modes 1 to 4 Read/Write —...
Page 274 Bits 7 to 4 are reserved. They cannot be modified and are always read as 1. P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 5 Input Pull-Up MOS Control Register (P5PCR): P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up MOS transistors in port 5.
Page 275: Overview
9.7 Port 6 9.7.1 Overview Port 6 is a 7-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, and WAIT). When DRAM is connected to area 3, LWR, HWR, and RD also function as LW, UW, and CAS, or LCAS, UCAS, and WE, respectively.
Page 276 Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. — P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR Initial value Read/Write —...
Page 277 Table 9-11 Port 6 Pin Functions in Modes 1 to 6 Pin Functions and Selection Method /LWR Functions as follows regardless of P6 LWR output Pin function /HWR Functions as follows regardless of P6 HWR output Pin function Functions as follows regardless of P6 RD output Pin function Functions as follows regardless of P6...
Page 278 9.8 Port 7 9.8.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 9-7 shows the pin configuration of port 7.
Page 279: Port 7
9.8.2 Register Description Table 9-12 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction register. Table 9-12 Port 7 Data Register Address* Name Abbreviation Initial Value H'FFCE Port 7 data register P7DR Undetermined Note: * Lower 16 bits of the address.
Page 280 9.9 Port 8 9.9.1 Overview output, RFSH output, and IRQ Port 8 is a 5-bit input/output port that is also used for CS to CS to IRQ input. Figure 9-8 shows the pin configuration of port 8. In modes 1 to 6 (expanded modes), port 8 can provide CS to CS output, RFSH output, and IRQ to IRQ...
Page 281 9.9.2 Register Descriptions Table 9-13 summarizes the registers of port 8. Table 9-13 Port 8 Registers Initial Value Address* Name Abbreviation Mode 1 to 4 Mode 5 to 7 H'FFCD Port 8 data direction P8DDR H'F0 H'E0 register H'FFCF Port 8 data register P8DR H'E0 H'E0...
Page 282 P8DDR is initialized to H'E0 or H'F0 by a reset and in hardware standby mode. The reset value depends on the operating mode. In software standby mode P8DDR retains its previous setting. If a P8DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data for pins P8 to P8...
Page 283 Table 9-14 Port 8 Pin Functions in Modes 1 to 6 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows Pin function input output /IRQ Bit P8 DDR selects the pin function as follows Pin function input output input...
Page 284 Table 9-15 Port 8 Pin Functions in Mode 7 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows Pin function input output /IRQ Bit P8 DDR selects the pin function as follows Pin function input output input /IRQ...
Page 285 9.10 Port 9 9.10.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD , SCK ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ and IRQ input.
Page 286 Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. — — P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR Initial value Read/Write —...
Page 287 Table 9-17 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P9 select the pin function as follows CKE1 — CKE0 — —...
Page 288 Table 9-17 Port 9 Pin Functions (cont) Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1 and bit P9 DDR select the pin function as follows — Pin function input output output /TxD Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows SMIF...
Page 289: Port A
9.11 Port A 9.11.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input and output (TIOCB , TIOCA , TIOCB , TIOCA , TIOCB TIOCA , TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU), output (TEND...
Page 290 Port A pins PA /TP /TIOCB /A PA /TP /TIOCA /A (output) PA /TP /TIOCB /A (output) PA /TP /TIOCA /A (output) Port A PA /TP /TIOCB /TCLKD PA /TP /TIOCA /TCLKC PA /TP /TEND /TCLKB PA /TP /TEND /TCLKA Pin functions in modes 1, 2, and 5 PA (input/output)/TP (output)/TIOCB (input/output) PA (input/output)/TP (output)/TIOCA (input/output)/CS...
Page 291: Register Descriptions
9.11.2 Register Descriptions Table 9-18 summarizes the registers of port A. Table 9-18 Port A Registers Initial Value Abbre- Address* Name viation Modes 1, 2, 5 and 7 Modes 3, 4, and 6 H'FFD1 Port A data direction PADDR H'00 H'80 register H'FFD3...
Page 292 Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for pins PA to PA . When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Page 293 Table 9-19 Port A Pin Functions (cont) Pin Functions and Selection Method / The mode setting, bit A E in BRCR, bit CS4E in CSCR, ITU channel 2 settings (bit TIOCA PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit DDR in PADDR select the pin function as follows Mode 1, 2, 5...
Page 294: Pin Functions
Table 9-19 Port A Pin Functions (cont) Pin Functions and Selection Method / The mode setting, bit A E in BRCR, bit CS6E in CSCR, ITU channel 1 settings (bit TIOCA PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit DDR in PADDR select the pin function as follows Mode 1, 2, 5...
Page 295 Table 9-19 Port A Pin Functions (cont) Pin Functions and Selection Method / ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TIOCA TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA DDR in PADDR TCLKC select the pin function as follows...
Page 296 Table 9-19 Port A Pin Functions (cont) Pin Functions and Selection Method / DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B), TCLKB/ bit NDER1 in NDERA, and bit PA DDR in PADDR select the pin function as follows TEND DMAC channel 1...
Page 297: Port B
9.12 Port B 9.12.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TIOCB , TIOCB , TIOCA TIOCA ) and output (TOCXB , TOCXA ) by the 16-bit integrated timer unit (ITU), input , DREQ...
Page 298 Port B pins /DREQ /ADTRG /DREQ /TOCXB /TOCXA Port B /TIOCB /TIOCA /TIOCB /TIOCA Pin functions in modes 1 to 6 (input/output)/TP (output)/DREQ (input)/ADTRG (input) (input/output)/TP (output)/DREQ (input)/CS (output) (input/output)/TP (output)/TOCXB (output) (input/output)/TP (output)/TOCXA (output) (input/output)/TP (output)/TIOCB (input/output) (input/output)/TP (output)/TIOCA (input/output) (input/output)/TP (output)/TIOCB...
Page 299: Register Descriptions
9.12.2 Register Descriptions Table 9-20 summarizes the registers of port B. Table 9-20 Port B Registers Address* Name Abbreviation Initial Value H'FFD4 Port B data direction register PBDDR H'00 H'FFD6 Port B data register PBDR H'00 Note: * Lower 16 bits of the address. Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B.
Page 300 Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins PB7 to PB0. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read.
Page 301: Pin Functions
9.12.3 Pin Functions Table 9-21 describes the selection of pin functions. Table 9-21 Port B Pin Functions Pin Functions and Selection Method DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B), bit TRGE in ADCR, bit NDER15 in NDERB, and bit PB DDR in PBDDR select the pin function as follows DREQ...
Page 302 Table 9-21 Port B Pin Functions (cont) Pin Functions and Selection Method Bit CS7E in CSCR, DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR0A and DTCR0B), bit NDER14 in NDERB, and bit PB DDR in PBDDR select the DREQ pin function as follows —...
Page 303 Table 9-21 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB DDR in PBDDR select TIOCB the pin function as follows...
Page 304 Table 9-21 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB DDR in PBDDR select TIOCA the pin function as follows...
Page 305 Table 9-21 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and TIOCB bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB DDR in PBDDR select the pin function as follows channel 3...
Page 306 Table 9-21 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and TIOCA bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB DDR in PBDDR select the pin function as follows channel 3...
Page 307: 16-Bit Integrated Timer Unit (Itu)
Section 10 16-Bit Integrated Timer Unit (ITU) 10.1 Overview The H8/3048 Series has a built-in 16-bit integrated timer unit (ITU) with five 16-bit timer channels. When the ITU is not used, it can be independently halted to conserve power. For details see section 20.6, Module Standby Function.
Page 308 — PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to five-phase PWM output is possible • Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. • Three additional modes selectable in channels 3 and 4 —...
Page 309 Table 10-1 summarizes the ITU functions. Table 10-1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Clock sources Internal clocks: ø, ø/2, ø/4, ø/8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3...
Page 310: Block Diagrams
10.1.2 Block Diagrams ITU Block Diagram (Overall): Figure 10-1 is a block diagram of the ITU. IMIA0 to IMIA4 TCLKA to TCLKD Clock selector IMIB0 to IMIB4 OVI0 to OVI4 ø, ø/2, ø/4, ø/8 Control logic TOCXA , TOCXB TIOCA to TIOCA TIOCB to TIOCB...
Page 311 Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 10-2. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 Control logic IMIA0 Comparator IMIB0 OVI0 Module data bus Legend TCNT:...
Page 312 Block Diagram of Channel 2: Figure 10-3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 Control logic IMIA2 Comparator IMIB2 OVI2...
Page 313 Block Diagrams of Channels 3 and 4: Figure 10-4 is a block diagram of channel 3. Figure 10-5 is a block diagram of channel 4. TIOCA TCLKA to TIOCB TCLKD Clock selector ø, ø/2, Control logic ø/4, ø/8 IMIA3 Comparator IMIB3 OVI3 Module data bus...
Page 314 TOCXA TCLKA to TOCXB TCLKD Clock selector ø, ø/2, TIOCA ø/4, ø/8 TIOCB Control logic IMIA4 Comparator IMIB4 OVI4 Module data bus Legend TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) ×...
Page 315: Input/Output Pins
10.1.3 Input/Output Pins Table 10-2 summarizes the ITU pins. Table 10-2 ITU Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input External clock B input pin...
Page 316: Register Configuration
10.1.4 Register Configuration Table 10-3 summarizes the ITU registers. Table 10-3 ITU Registers Abbre- Initial Channel Address Name viation Value Common H'FF60 Timer start register TSTR H'E0 H'FF61 Timer synchro register TSNC H'E0 H'FF62 Timer mode register TMDR H'80 H'FF63 Timer function control register TFCR H'C0...
Page 317 Table 10-3 ITU Registers (cont) Abbre- Initial Channel Address Name viation Value H'FF78 Timer control register 2 TCR2 H'80 H'FF79 Timer I/O control register 2 TIOR2 H'88 H'FF7A Timer interrupt enable register 2 TIER2 H'F8 H'FF7B Timer status register 2 TSR2 R/(W) H'F8...
Page 318 Table 10-3 ITU Registers (cont) Abbre- Initial Channel Address Name viation Value H'FF92 Timer control register 4 TCR4 H'80 H'FF93 Timer I/O control register 4 TIOR4 H'88 H'FF94 Timer interrupt enable register 4 TIER4 H'F8 H'FF95 Timer status register 4 TSR4 R/(W) H'F8...
Page 319: Register Descriptions
10.2 Register Descriptions 10.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 4. — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — —...
Page 320: Timer Synchro Register (Tsnc)
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1). Bit 1 STR1 Description TCNT1 is halted (Initial value) TCNT1 is counting Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0). Bit 0 STR0 Description TCNT0 is halted (Initial value) TCNT0 is counting...
Page 321 Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or synchronously. Bit 3 SYNC3 Description Channel 3’s timer counter (TCNT3) operates independently (Initial value) TCNT3 is preset and cleared independently of other channels Channel 3 operates synchronously TCNT3 can be synchronously preset and cleared Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously.
Page 322: Timer Mode Register (Tmdr)
10.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. — FDIR PWM4 PWM3 PWM2 PWM1 PWM0...
Page 323 When MDF is set to 1 to select phase counting mode, TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction Down-Counting Up-Counting...
Page 324 Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode. Bit 3 PWM3 Description Channel 3 operates normally (Initial value) Channel 3 operates in PWM mode When bit PWM3 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
Page 325: Timer Function Control Register (Tfcr)
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. Bit 0 PWM0 Description Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode When bit PWM0 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
Page 326 Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels 3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode. Bit 5 Bit 4 CMD1 CMD0 Description Channels 3 and 4 operate normally (Initial value) Channels 3 and 4 operate together in complementary PWM mode Channels 3 and 4 operate together in reset-synchronized PWM mode...
Page 327: Timer Output Master Enable Register (Toer)
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or whether GRB3 is buffered by BRB3. Bit 1 BFB3 Description GRB3 operates normally (Initial value) GRB3 is buffered by BRB3 Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or whether GRA3 is buffered by BRA3.
Page 328 Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB Bit 5 EXB4 Description TOCXB output is disabled regardless of TFCR settings (TOCXB operates as a generic input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1. TOCXB is enabled for output according to TFCR settings (Initial value)
Page 329 Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB Bit 2 Description TIOCB output is disabled regardless of TIOR4 and TFCR settings (TIOCB operates as a generic input/output pin). If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1. TIOCB is enabled for output according to TIOR4 and TFCR settings (Initial value)
Page 330: Timer Output Control Register (Tocr)
10.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. — — — XTGD — — OLS4 OLS3 Initial value Read/Write —...
Page 331: Timer Counters (Tcnt)
Bits 3 and 2—Reserved: Read-only bits, always read as 1. Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 Description TIOCA , TIOCA , and TIOCB outputs are inverted TIOCA , TIOCA , and TIOCB...
Page 332: General Registers (Gra, Grb)
TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM mode and up-counters in other modes. TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA or GRB (counter clearing function) in the same channel.
Page 333: Buffer Registers (Bra, Brb)
When a general register is used as an input capture register, rising edges, falling edges, or both edges of an external input capture signal are detected and the current TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR.
Page 334: Timer Control Registers (Tcr)
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. 10.2.10 Timer Control Registers (TCR) TCR is an 8-bit register.
Page 335 Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by GRA compare match or input capture TCNT is cleared by GRB compare match or input capture Synchronous clear: TCNT is cleared in synchronization with other synchronized timers Notes: 1.
Page 336: Timer I/O Control Register (Tior)
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 Function Internal clock: ø (Initial value) Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input...
Page 337 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins.
Page 338: Timer Status Register (Tsr)
Bit 3—Reserved: Read-only bit, always read as 1. Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 Function GRA is an output No output at compare match (Initial value) compare register 0 output at GRA compare match...
Page 339 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Reserved bits Overflow flag Status flag indicating overflow or underflow Input capture/compare match flag B Status flag indicating GRB compare match or input capture Input capture/compare match flag A Status flag indicating GRA compare match or input capture...
Page 340 Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB compare match or input capture events. Bit 1 IMFB Description [Clearing condition] (Initial value) Read IMFB when IMFB = 1, then write 0 in IMFB [Setting conditions] TCNT = GRB when GRB functions as an output compare register. TCNT value is transferred to GRB by an input capture signal, when GRB functions as an input capture register.
Page 341: Timer Interrupt Enable Register (Tier)
10.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel Abbreviation Function TIER0 Enables or disables interrupt requests. TIER1 TIER2 TIER3 TIER4 — — — — — OVIE IMIEB IMIEA Initial value Read/Write...
Page 342 Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the OVF flag in TSR when OVF is set to 1. Bit 2 OVIE Description OVI interrupt requested by OVF is disabled (Initial value) OVI interrupt requested by OVF is enabled Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Page 343: Cpu Interface
10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus.
Page 344 On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 10-8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 10-9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) On-chip data bus Module Bus interface...
Page 345: 8-Bit Accessible Registers
On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 10-11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 10.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 10-12 and 10-13 show examples of byte read and write access to a TCR.
Page 346 On-chip data bus Module Bus interface data bus Figure 10-13 Access to Timer Counter (CPU Reads TCR)
Page 347: Operation
10.4 Operation 10.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare.
Page 348: Basic Functions
Buffering • If the general register is an output compare register When compare match occurs the buffer register value is transferred to the general register. • If the general register is an input capture register When input capture occurs the TCNT value is transferred to the general register, and the previous general register value is transferred to the buffer register.
Page 349 Counter setup Select counter clock Type of counting? Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter Figure 10-14 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal.
Page 350 • Free-running and periodic counter operation A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TSR.
Page 351 TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 10-16 Periodic Counter Operation • TCNT count timing — Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (ø) or one of three internal clock sources obtained by prescaling the system clock (ø/2, ø/4, ø/8).
Page 352 — External clock source Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected.
Page 353 Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
Page 354 TCNT value H'FFFF H'0000 Time TIOCB No change No change 1 output No change No change 0 output TIOCA Figure 10-20 0 and 1 Output (Examples) Figure 10-21 shows examples of toggle output. TCNT operates as a periodic counter, cleared by compare match B.
Page 355 • Output compare timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 356 Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the port data direction bit to 0 before making these TIOR settings. Select input-capture input Start counter Set the STR bit to 1 in TSTR to start the timer...
Page 357 • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 10-25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 358 10.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
Page 359 Example of Synchronization: Figure 10-27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0.
Page 360 10.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
Page 361 Sample Setup Procedure for PWM Mode: Figure 10-28 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to Select counter clock select the desired edge(s) of the...
Page 362 Examples of PWM Mode: Figure 10-29 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible.
Page 363 Figure 10-30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
Page 364 10.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA TIOCB , and TOCXB...
Page 365 Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 10-31 shows a sample procedure for setting up reset-synchronized PWM mode. Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode must be set up while TCNT3 is halted.
Page 366 Example of Reset-Synchronized PWM Mode: Figure 10-32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000. The PWM outputs toggle at compare match of TCNT3 with GRB3, GRA4, and GRB4 respectively, and all toggle when the counter is cleared.
Page 367 10.4.6 Complementary PWM Mode In complementary PWM mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping PWM waveforms. When complementary PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA , TIOCB and TOCXB automatically become PWM output pins, and TCNT3 and TCNT4 function as up/down-counters.
Page 368 Setup Procedure for Complementary PWM Mode: Figure 10-33 shows a sample procedure for setting up complementary PWM mode. Complementary PWM mode 1. Clear bits STR3 and STR4 to 0 in TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are Stop counting halted.
Page 369 Clearing Procedure for Complementary PWM Mode: Figure 10-34 shows the steps to clear complementary PWM mode. Complementary PWM mode 1. Clear the CMD1 bit of TFCR to 0 to set channels 3 and 4 to normal operating mode. 2. After setting channels 3 and 4 to Clear complementary PWM mode normal operating mode, wait at least one counter clock period, then clear...
Page 370 Examples of Complementary PWM Mode: Figure 10-35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4 underflows. During each up-and-down counting cycle, PWM waveforms are generated by compare match with general registers GRB3, GRA4, and GRB4.
Page 371 Figure 10-36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example the outputs change at compare match with GRB3, so waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than GRA3.
Page 372 In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer conditions also differ.
Page 373 Underflow Overflow TCNT4 H'0001 H'0000 H'FFFF H'0000 Flag not set Set to 1 Buffer transfer signal (BR to GR) Buffer transfer No buffer transfer Figure 10-38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs.
Page 374 GRA3 H'0000 Not allowed Figure 10-39 Changing a General Register Setting by Buffer Transfer (Example 1) — Buffer transfer at transition from up-counting to down-counting If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a buffer register value outside this range.
Page 375 — Buffer transfer at transition from down-counting to up-counting If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer register value outside this range. Conversely, when a general register value is outside this range, do not transfer a value within this range.
Page 376 — General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range. When a buffer register is set to a value outside the counting range, then later restored to a value within the counting range, the counting direction (up or down) must be the same both times.
Page 377: Phase Counting Mode
10.4.7 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2.
Page 378 Example of Phase Counting Mode: Figure 10-44 shows an example of operations in phase counting mode. Table 10-9 lists the up-counting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 379: Buffering
10.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations under the conditions mentioned above are described next.
Page 380 • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. This occurs at the following two times: — When TCNT3 compare matches GRA3 — When TCNT4 underflows • Reset-synchronized PWM mode The buffer register value is transferred to the general register at compare match A3.
Page 381 Examples of Buffering: Figure 10-49 shows an example in which GRA is set to function as an output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA.
Page 382 ø TCNT n + 1 Compare match signal Buffer transfer signal Figure 10-50 Compare Match and Buffer Transfer Timing (Example)
Page 383 Figure 10-51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous GRA value is simultaneously transferred to BRA.
Page 384 ø TIOC pin Input capture signal TCNT n + 1 N + 1 Figure 10-52 Input Capture and Buffer Transfer Timing (Example)
Page 385 Figure 10-53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows.
Page 386: Itu Output Timing
10.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER.
Page 387 Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output.
Page 388: Interrupts
10.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 10.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR).
Page 389 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 10-58 shows the timing. ø Input capture signal TCNT Figure 10-58 Timing of Setting of IMFA and IMFB by Input Capture...
Page 390: Clearing Of Status Flags
ø TCNT H'FFFF H'0000 Overflow signal Figure 10-59 Timing of Setting of OVF 10.5.2 Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared.
Page 391: Interrupt Sources And Dma Controller Activation
10.5.3 Interrupt Sources and DMA Controller Activation Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored. An interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1.
Page 392: Usage Notes
10.6 Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear: If a counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 10-61.
Page 393 Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 10-62. TCNT word write cycle ø Address bus TCNT address Internal write signal TCNT input clock...
Page 394 Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 10-63, which shows an increment pulse occurring in the T state of a byte write to TCNTH.
Page 395 Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 10-64. General register write cycle ø...
Page 396 Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 10-65. TCNT write cycle ø...
Page 397 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 10-66. General register read cycle ø GR address Address bus Internal read signal Input capture signal...
Page 398 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 399 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 10-68. General register write cycle ø...
Page 400 Contention between Buffer Register Write and Input Capture: If a buffer register is used for input capture buffering and an input capture signal occurs in the T state of a write cycle, input capture takes priority and the write to the buffer register is not performed. See figure 10-69.
Page 401 Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 2 and 3 are synchronized •...
Page 407: Programmable Timing Pattern Controller
Section 11 Programmable Timing Pattern Controller 11.1 Overview The H8/3048 Series has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit integrated timer unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 408: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the TPC. ITU compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output pins, group 1 PADR NDRA...
Page 409: Tpc Pins
11.1.3 TPC Pins Table 11-1 summarizes the TPC output pins. Table 11-1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output Group 1 pulse output TPC output 5...
Page 410: Registers
11.1.4 Registers Table 11-2 summarizes the TPC registers. Table 11-2 TPC Registers Address Name Abbreviation Initial Value H'FFD1 Port A data direction register PADDR H'00 H'FFD3 Port A data register PADR R/(W) H'00 H'FFD4 Port B data direction register PBDDR H'00 H'FFD6 Port B data register...
Page 411: Register Descriptions
11.2 Register Descriptions 11.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Read/Write...
Page 412: Port B Data Direction Register (Pbddr)
11.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7 to 0...
Page 413: Next Data Register A (Ndra)
11.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 414 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that cannot be modified and are always read as 1.
Page 415: Next Data Register B (Ndrb)
11.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 416 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that cannot be modified and are always read as 1.
Page 417: Next Data Enable Register A (Ndera)
11.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value Read/Write Next data enable 7 to 0 These bits enable or disable...
Page 418: Next Data Enable Register B (Nderb)
11.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 These bits enable or disable...
Page 419: Tpc Output Control Register (Tpcr)
11.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare...
Page 420 Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP to TP Bit 7 Bit 6 G3CMS1 G3CMS0 Description TPC output group 3 (TP to TP ) is triggered by compare match in ITU channel 0...
Page 421 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP to TP Bit 3 Bit 2 G1CMS1 G1CMS0 Description TPC output group 1 (TP to TP ) is triggered by compare match in ITU channel 0...
Page 422: Tpc Output Mode Register (Tpmr)
11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP to TP )
Page 423 Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected ITU channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected ITU channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for...
Page 424: Operation
11.3 Operation 11.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 425: Output Timing
11.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...
Page 426: Normal Tpc Output
11.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 11-4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited). Set the TPC output trigger period.
Page 427 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR • The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
Page 428: Non-Overlapping Tpc Output
11.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11-6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited). Set the TPC output trigger period in GRB Set GR values and the non-overlap margin in GRA.
Page 429 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11-7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR Non-overlap margin This operation example is described below. •...
Page 430: Tpc Output Triggering By Input Capture
11.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 431: Usage Notes
11.4 Usage Notes 11.4.1 Operation of TPC Output Pins to TP are multiplexed with ITU, DMAC, address bus, and other pin functions. When ITU, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Page 432 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC.
Page 433: Watchdog Timer
Section 12 Watchdog Timer 12.1 Overview The H8/3048 Series has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. As a watchdog timer, it generates a reset signal for the chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten.
Page 434: Block Diagram
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources ø/2 RSTCSR ø/32 ø/64 Reset Reset control Clock ø/128 (internal, external) Clock selector ø/256...
Page 435: Register Configuration
12.1.4 Register Configuration Table 12-2 summarizes the WDT registers. Table 12-2 WDT Registers Address Write Read Name Abbreviation Initial Value H'FFA8 H'FFA8 Timer control/status register TCSR R/(W) H'18 H'FFA9 Timer counter TCNT H'00 H'FFAA H'FFAB Reset control/status register RSTCSR R/(W) H'3F Notes: 1.
Page 436: Register Descriptions
12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable* up-counter. Initial value Read/Write When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR.
Page 437: Timer Control/Status Register (Tcsr)
12.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source Reserved bits Timer enable...
Page 438 Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value) [Setting condition] Set when TCNT changes from H'FF to H'00 Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or...
Page 439: Reset Control/Status Register (Rstcsr)
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (ø), for input to TCNT. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description ø/2 (Initial value) ø/32 ø/64...
Page 440 Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices.
Page 441: Notes On Register Access
12.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions.
Page 442 Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 12-3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 443: Operation
12.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 12.3.1 Watchdog Timer Operation Figure 12-4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR.
Page 444: Interval Timer Operation
12.3.2 Interval Timer Operation Figure 12-5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow.
Page 445: Timing Of Setting Of Overflow Flag (Ovf)
12.3.3 Timing of Setting of Overflow Flag (OVF) Figure 12-6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
Page 446: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 12-7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1.
Page 447: Interrupts
12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 448: Serial Communication Interface
Section 13 Serial Communication Interface 13.1 Overview The H8/3048 Series has a serial communication interface (SCI) with two independent channels. The two channels are functionally identical. The SCI can communicate in asynchronous or synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 449 Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. — Data length: 8 bits — Receive error detection: overrun errors •...
Page 450: Block Diagram
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the SCI. Internal data bus Module data bus ø Baud rate ø/4 generator Transmit/ ø/16 receive control ø/64 Parity generate Clock Parity check External clock Legend RSR: Receive shift register RDR: Receive data register TSR:...
Page 451: Input/Output Pins
13.1.3 Input/Output Pins The SCI has serial pins for each channel as listed in table 13-1. Table 13-1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output Serial clock pin...
Page 452: Register Descriptions
13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. Read/Write — — — — — — — — The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 453: Transmit Shift Register (Tsr)
13.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Read/Write — — — — — — — — The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it.
Page 454: Serial Mode Register (Smr)
13.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator’s clock source Multiprocessor mode...
Page 455 Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 Description Asynchronous mode (Initial value) Synchronous mode Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6 Description 8-bit data...
Page 456 Bit 4—Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is valid in asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit. The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled in asynchronous mode.
Page 457: Section 13.2.8, Bit Rate Register (Brr)
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication.
Page 458: Serial Control Register (Scr)
13.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1/0 These bits select the SCI clock source Transmit-end interrupt enable...
Page 459 Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 Description Transmit-data-empty interrupt request (TXI) is disabled* (Initial value) Transmit-data-empty interrupt request (TXI) is enabled Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then...
Page 460 Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 Description Receiving disabled (Initial value) Receiving enabled Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 461 Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2 TEIE Description Transmit-end interrupt requests (TEI) are disabled* (Initial value) Transmit-end interrupt requests (TEI) are enabled* Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0;...
Page 462: Serial Status Register (Ssr)
13.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer Value of multi- processor bit to be transmitted Multiprocessor bit...
Page 463 The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written.
Page 464 Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally (Initial value) [Clearing conditions] The chip is reset or enters standby mode. Software reads ORER while it is set to 1, then writes 0. A receive overrun error occurred [Setting condition] Reception of the next serial data ends when RDRF = 1.
Page 465 Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 Description Receiving is in progress or has ended normally (Initial value) [Clearing conditions] The chip is reset or enters standby mode. Software reads PER while it is set to 1, then writes 0.
Page 466: Bit Rate Register (Brr)
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value) Multiprocessor bit value in receive data is 1 Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its...
Page 467 Table 13-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode ø (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.16 0.16 0.21 0.16 0.16 0.21 0.16 1200 0.16 –0.70 0.16 2400 0.16 1.14...
Page 468 Table 13-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 2400 0.16 0.16 4800 0.16 0.16...
Page 469 Table 13-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 14.7456 Bit Rate Error Error Error Error (bits/s) –0.08 –0.17 0.70 0.03 0.16 0.16 0.16 –0.43 0.16 0.16 0.16 0.16 0.16 1200 –0.43 0.16 0.16 2400 0.16 0.16...
Page 470 Table 13-4 Examples of Bit Rates and BRR Settings in Synchronous Mode ø (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — — — — — — — 2.5 k 10 k 25 k 50 k 100 k...
Page 471 SMR Settings Clock Source CKS1 CKS0 ø ø/4 ø/16 ø/64 The bit rate error in asynchronous mode is calculated as follows. ø × 10 –1 × 100 Error (%) = (N + 1) × B × 64 × 2 2n–1...
Page 472 Table 13-5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 13-6 and 13-7 indicate the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings ø (MHz) Maximum Bit Rate (bits/s) 62500 2.097152...
Page 473 Table 13-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 474 Table 13-7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0...
Page 475: Operation
13.3 Operation 13.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous or synchronous mode and the communication format are selected in SMR, as shown in table 13-8.
Page 476 Table 13-8 SMR Settings and Serial Communication Formats SCI Communication Format SMR Settings Multi- Stop Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data processor Parity CHR MP STOP Mode Length Length Asynchronous 8-bit data Absent Absent 1 bit mode 2 bits Present...
Page 477: Operation In Asynchronous Mode
13.3.2 Operation in Asynchronous Mode In asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Page 478 Communication Formats: Table 13-10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 13-10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data...
Page 479 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 13-9. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate.
Page 480 Start of initialization Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after Clear TE and RE bits the setting is made in SCR. to 0 in SCR Select the communication format in SMR.
Page 481 Transmitting Serial Data (Asynchronous Mode): Figure 13-5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, Start transmitting check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0.
Page 482 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 483 Receiving Serial Data (Asynchronous Mode): Figure 13-7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. 2, 3. Receive error handling and break Start receiving detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify...
Page 484 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR PER = 1? Parity error handling Clear ORER, PER, and FER flags to 0 in SSR Figure 13-7 Sample Flowchart for Receiving Serial Data (2)
Page 485 In receiving, the SCI operates as follows. • The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 486: Multiprocessor Communication
Figure 13-8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt handler request reads data in RDR and Framing error, clears RDRF flag to 0 ERI request 1 frame Figure 13-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
Page 487 Communication Formats: Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 13-10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01)
Page 488 Transmitting and Receiving Data Transmitting Multiprocessor Serial Data: Figure 13-10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE...
Page 489 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 490 Receiving Multiprocessor Serial Data: Figure 13-12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read Set MPIE bit to 1 in SCR...
Page 491 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR Clear ORER, PER, and FER flags to 0 in SSR Figure 13-12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
Page 492 Figure 13-13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value MPB detection RXI request RXI handler reads Not own ID, so No RXI request, MPIE= 0 (multiprocessor RDR data and clears...
Page 493: Synchronous Operation
13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible.
Page 494 Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 495 Transmitting Serial Data (Synchronous Mode): Figure 13-16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. After setting TE bit to 1, output 1 from frame one transmission is possible.
Page 496 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 497 Figure 13-17 shows an example of SCI transmit operation. Transmit direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt handler request writes data in TDR request request and clears TDRE flag to 0...
Page 498 Receiving Serial Data: Figure 13-18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 499 Error handling Overrun error handling Clear ORER flag to 0 in SSR Figure 13-18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. • The SCI synchronizes with serial clock input or output and initializes internally. •...
Page 500 Figure 13-19 shows an example of SCI receive operation. Receive direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request handler reads Overrun error, request data in RDR ERI request and clears RDRF flag to 0...
Page 501 SCI initialization: the transmit data output function of the TxD pin and Initialize receive data input function of the RxD pin are selected, enabling Start transmitting and receiving simultaneous transmitting and receiving. SCI status check and transmit data write: read SSR, check that Read TDRE flag in SSR the TDRE flag is 1, then write transmit data in TDR and clear...
Page 502: Sci Interrupts
13.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 13-12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, TEIE, and RIE bits in SCR.
Page 503: Usage Notes
13.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 504 Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Page 505 16 clocks 8 clocks 15 0 15 0 Internal base clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as in equation (1). | D –...
Page 506 Restrictions on Usage of DMAC To have the DMAC read RDR, be sure to select the SCI receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR. Restrictions on Usage of the Serial Clock When transmitting data using the serial clock as an external clock, after clearing SSR of TDRE, maintain the space between each frame of the lead of the transmission clock (start-up edge) at five states or more (see Figure 13-22).
Page 507: Smart Card Interface
Section 14 Smart Card Interface 14.1 Overview As an extension of its serial communication interface functions, SCI0 supports a smart card (IC card) interface conforming to the ISO/IEC7816-3 (Identification Card) standard. Switchover between normal serial communication and the smart card interface is controlled by a register setting.
Page 508: Block Diagram
14.1.2 Block Diagram Figure 14-1 shows a block diagram of the smart card interface. Internal data Module data bus SCMR ø ø/4 ø/16 Transmit/receive Baud rate ø/64 control generator Parity generate Clock Parity check Legend Smart card mode register SCMR: RSR: Receive shift register RDR:...
Page 509: Input/Output Pins
14.1.3 Input/Output Pins Table 14-1 lists the smart card interface pins. Table 14-1 Smart Card Interface Pins Name Abbreviation Function Serial clock pin Output Clock output Receive data pin Input Receive data input Transmit data pin Output Transmit data output 14.1.4 Register Configuration The smart card interface has the internal registers listed in table 14-2.
Page 510: Register Descriptions
14.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 14.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. — — — —...
Page 511: Serial Status Register (Ssr)
Bit 2—Smart Card Data Inverter (SINV): Inverts data logic levels. This function is used in combination with bit 3 to communicate with inverse-convention cards. SINV does not affect the logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings. Bit 2 SINV Description...
Page 512 Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13, Serial Communication Interface. Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device. The smart card interface does not detect framing errors.
Page 513: Serial Mode Register (Smr)
14.2.3 Serial Mode Register (SMR) Bit 7 of SMR has a different function in smart card interface mode. The related serial control register (SCR) changes from bit 1 to bit 0. However, this function does not exist in the flash memory version.
Page 514: Serial Control Register (Scr)
14.2.4 Serial Control Register (SCR) Bits 1 and 0 have different functions in smart card interface mode. However, this function does not exist in the flash memory version. MPIE TEIE CKE1 CKE0 Initial value Read/Write Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 13.2.6, Serial Control Register (SCR).
Page 515: Operation
14.3 Operation 14.3.1 Overview The main features of the smart-card interface are as follows. • One frame consists of eight data bits and a parity bit. • In transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of the next frame.
Page 516: Data Format
Data line Clock line Px (port) H8/3048 Series Reset line Smart card Chip Card-processing device Figure 14-2 Smart Card Interface Connection Diagram Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a smart card.
Page 517 The operating sequence is as follows. 1. When not in use, the data line is in the high-impedance state, and is pulled up to the high level through a resistor. 2. To start transmitting a frame of data, the transmitting device transmits a low start bit (Ds), followed by eight data bits (D0 to D7) and a parity bit (Dp).
Page 518: Register Settings
14.3.4 Register Settings Table 14-3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 should always be set to the indicated value. The settings of the other bits will be described in this section.
Page 519 The register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. Direct convention (SDIR = SINV = O/E = 0) State In the direct convention, state Z corresponds to logic level 1, and state A to logic level 0. Characters are transmitted and received LSB-first.
Page 520: Clock
14.3.5 Clock As its serial communication clock, the smart card interface can use only the internal clock generated by the on-chip baud rate generator. The bit rate can be selected by setting the bit rate register (BRR) and bits CKS1 and CKS0 in the serial mode register (SMR). The bit rate can be calculated from the equation given below.
Page 521 The following equation calculates the bit rate register (BRR) setting from the system clock frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. ø × 10 – 1 1488 × 2 ×...
Page 522: Transmitting And Receiving Data
14.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, initialize the smart card interface by the procedure below. Initialization is also necessary when switching from transmit mode to receive mode or from receive mode to transmit mode. 1. Clear the TE and RE bits to 0 in the serial control register (SCR). 2.
Page 523 TEND flag is set to 1, a transmit-data-empty interrupt (TXI) is requested. If the RIE bit is set to 1 to enable interrupt requests, when a transmit error occurs and the ERS flag is set to 1, a transmit/receive-error interrupt (ERI) is requested. The timing of TEND flag setting depends on the GM bit in SMR.
Page 524 (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output (3) Serial data output Data 1 In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 525 Receiving Serial Data: The receiving procedure in smart card mode is the same as the normal SCI procedure. Figure 14-7 shows a flowchart for receiving. 1. Initialize the smart card interface by the procedure given in Initialization at the beginning of this section.
Page 526 This procedure may include interrupt handling and DMA transfer. If the RIE bit is set to 1 to enable interrupt requests, when receiving is completed and the RDRF flag is set to 1, a receive-data-full interrupt (RXI) is requested. If a receive error occurs, either the ORER or PER flag is set to 1 and a transmit/receive-error interrupt (ERI) is requested.
Page 527 A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or ERS flag is set to 1 in SSR.
Page 528 2. Write 0 to the TE and RE bits in the serial control register (SCR) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4.
Page 529: Usage Notes
14.4 Usage Notes When using the SCI as a smart card interface, note the following points. Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card mode the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock.
Page 530 The receive margin can therefore be expressed as follows. Receive margin in smart card mode: | D – 0.5 | M = | (1 + F) | × 100% 0.5 – – (L – 0.5) F – M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 10)
Page 531 Retransmission: Retransmission is described below for the separate cases of transmit mode and receive mode. Retransmission when SCI is in Receive Mode (See Figure 14-11): (1) The SCI checks the received parity bit. If it detects an error, it automatically sets the PER flag to 1.
Page 532 Retransmission when SCI is in Transmit Mode (See Figure 14-12): (6) After transmitting one frame, if the receiving device returns an error signal, the SCI sets the ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested.
Page 533: A/D Converter
Section 15 A/D Converter 15.1 Overview The H8/3048 Series includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 20.6, Module Standby Function.
Page 534: Block Diagram
15.1.2 Block Diagram Figure 15-1 shows a block diagram of the A/D converter. On-chip Module data bus data bus 10-bit D/A – ø/8 Comparator Analog Control circuit multi- plexer Sample-and- ø/16 hold circuit ADTRG Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A...
Page 535: Input Pins
15.1.3 Input Pins Table 15-1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter. V is the A/D conversion reference voltage.
Page 536: Register Configuration
15.1.4 Register Configuration Table 15-2 summarizes the A/D converter’s registers. Table 15-2 A/D Converter Registers Address Name Abbreviation Initial Value H'FFE0 A/D data register A (high) ADDRAH H'00 H'FFE1 A/D data register A (low) ADDRAL H'00 H'FFE2 A/D data register B (high) ADDRBH H'00 H'FFE3...
Page 537: Register Descriptions
15.2 Register Descriptions 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ADDRn — — — — — — Initial value Read/Write (n = A to D) A/D conversion data Reserved bits 10-bit data giving an A/D conversion result The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 538: A/D Control/Status Register (Adcsr)
15.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts...
Page 539 Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 Description [Clearing condition] (Initial value) Cleared by reading ADF while ADF = 1, then writing 0 in ADF [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion.
Page 540 Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN Description Single mode (Initial value) Scan mode Bit 3—Clock Select (CKS): Selects the A/D conversion time.
Page 541: A/D Control Register (Adcr)
15.2.3 A/D Control Register (ADCR) TRGE — — — — — — — Initial value Read/Write — — — — — — — Reserved bits Trigger enable Enables or disables external triggering of A/D conversion ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion.
Page 542: Cpu Interface
15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows.
Page 543: Operation
15.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 544 Figure 15-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Page 545: Scan Mode (Scan = 1)
15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 546 Figure 15-4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected)
Page 547: Input Sampling And A/D Conversion Time
15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 15-5 shows the A/D conversion timing.
Page 548: External Trigger Input Timing
Table 15-4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 549: Interrupts
15.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 15.6 Usage Notes When using the A/D converter, note the following points: 1.
Page 550 6. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog input pins (AN to AN ) and analog reference voltage pin (V ), connect a protection circuit like the one in figure 15-7 between AV and AV .
Page 551 10 kΩ to AN To A/D converter 20 pF Note: Numeric values are approximate. Figure 15-8 Analog Input Pin Equivalent Circuit Table 15-5 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance — kΩ ≤ 12 MHz. ø...
Page 552 Digital output Ideal A/D conversion characteristic Quantization error 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Figure 15-9 A/D Converter Accuracy Definitions (1)
Page 553 Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog input Offset error voltage Figure 15-10 A/D Converter Accuracy Definitions (2) 8. Allowable Signal-Source Impedance: The analog inputs of the H8/3048 Series are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 kΩ.
Page 554 H8/3048 Series Equivalent circuit of A/D converter Sensor output impedance 10 kΩ Up to 10 kΩ Sensor input Cin = Low-pass 20 pF 15 pF filter Up to 0.1 µF Figure 15-11 Analog Input Circuit (Example)
Page 555: D/A Converter
Section 16 D/A Converter 16.1 Overview The H8/3048 Series includes a D/A converter with two channels. 16.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20-pF capacitive load) •...
Page 556: Input/Output Pins
16.1.3 Input/Output Pins Table 16-1 summarizes the D/A converter’s input and output pins. Table 16-1 D/A Converter Pins Pin Name Abbreviation Function Analog power supply pin Input Analog power supply Analog ground pin Input Analog ground and reference voltage Analog output pin 0 Output Analog output, channel 0 Analog output pin 1...
Page 557: Register Descriptions
16.2 Register Descriptions 16.2.1 D/A Data Registers 0 and 1 (DADR0/1) Initial value Read/Write The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 558 Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description analog output is disabled Channel-1 D/A conversion and DA analog output are enabled Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description...
Page 559: D/A Standby Control Register (Dastcr)
16.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode. — — — — — — DASTE — Initial value Read/Write — — — — — — — Reserved bits D/A standby enable Enables or disables D/A output...
Page 560: Operation
16.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1.
Page 561: D/A Output Control
16.4 D/A Output Control In the H8/3048 Series, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode. The D/A converter registers retain the values they held prior to the transition to software standby mode.
Page 562: Ram
Section 17 RAM 17.1 Overview The H8/3048 and H8/3047 have 4 kbytes of high-speed static RAM on-chip. The H8/3045 and H8/3044 have 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer.
Page 563: Register Configuration
17.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 17-1 gives the address and initial value of SYSCR. Table 17-1 System Control Register Address* Name Abbreviation Initial Value H'FFF2 System control register SYSCR H'0B Note: * Lower 16 bits of the address.
Page 564: System Control Register (Syscr)
17.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is enabled or disabled by the RAME bit in SYSCR.
Page 565: Operation
17.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF10 to H'FFF0F in the H8/3048 and H8/3047 in modes 1, 2, 5, and 7, addresses H'FFEF10 to H'FFFF0F in the H8/3048 and H8/3047 in modes 3, 4, and 6, addresses H'FF710 to H'FFF0F in the H8/3045 and H8/3044 in modes 1, 2, 5, and 7, and addresses H'FFF710 to H'FFFF0F in the H8/3045 and H8/3044 in modes 3, 4, and 6 are directed to the on-chip RAM.
Page 566: Rom
Section 18 ROM 18.1 Overview The H8/3048 has 128 kbytes of on-chip ROM, the H8/3047 has 96 kbytes, the H8/3045 has 64 kbytes and the H8/3044 has 32 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, enabling rapid data transfer.
Page 567: Block Diagram
18.1.1 Block Diagram Figure 18-1 shows a block diagram of the ROM. On-chip data bus (upper 8 bits) On-chip data bus (lower 8 bits) Bus interface H'0000 H'0001 H'0002 H'0003 On-chip ROM H'1FFFE H'1FFFF Even addresses Odd addresses Figure 18-1 ROM Block Diagram (H8/3048, Mode 7)
Page 568: Prom Mode
18.2 PROM Mode 18.2.1 PROM Mode Setting In PROM mode, the H8/3048 version with on-chip PROM suspends its microcontroller functions, enabling the on-chip PROM to be programmed. The programming method is the same as for the HN27C101, except that page programming is not supported. Table 18-2 indicates how to select PROM mode.
Page 569 H8/3048 PROM Socket FP-100B, TFP-100B HN27C101 (32 Pins) RESO STBY Legend Programming voltage (12.5 V) EO to EO : Data input/output to EA : Address input Output enable Chip enable PGM: Program Note: Pins not shown in this diagram should be left open. This figure shows pin assignments, and does not show the entire socket adapter circuit.
Page 570 Address in Address in MCU mode PROM mode H'00000 H'00000 On-chip PROM H'1FFFF H'1FFFF Figure 18-3 H8/3048 Memory Map in PROM Mode...
Page 571: Prom Programming
18.3 PROM Programming Table 18-4 indicates how to select the program, verify, and other modes in PROM mode. Table 18-4 Mode Selection in PROM Mode Pins Mode to EO to EA Program Data input Address input Verify Data output Address input Program inhibited High impedance Address input...
Page 572 Start Set programming/verification mode = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V Address = 0 n = 0 → n + 1 < Program with t = 0.2 ms ± 5% → Address + 1 address Verification OK? Program with t...
Page 573 Table 18-5 DC Characteristics (Conditions: V = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V, V = 0 V, T = 25°C ± 5°C) Item Symbol Unit Test Conditions Input high to EO — + 0.3 voltage to EA OE, CE, PGM...
Page 574 Table 18-6 AC Characteristics (Conditions: V = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V, T = 25°C ± 5°C) Item Symbol Unit Test Conditions Address setup time — — µs Figure 18-5 OE setup time —...
Page 575 Program Verify Address Data Input data Output data Note: is defined by the value given in the flowchart. Figure 18-5 PROM Program/Verify Timing...
Page 576: Programming Precautions
) in PROM mode is 12.5 V. Applied voltages in excess of the rated values can permanently destroy the chip. Be particularly careful about the PROM programmer’s overshoot characteristics. If the PROM programmer is set to Hitachi HN27C101 specifications, V will be 12.5 V. •...
Page 577: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 578: Flash Memory Overview
18.4 Flash Memory Overview 18.4.1 Flash Memory Operation Table 18-7 illustrates the principle of operation of the H8/3048F’s on-chip flash memory. Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a programmed memory cell is therefore higher than that of an erased cell.
Page 579: Mode Programming And Flash Memory Address Space
18.4.2 Mode Programming and Flash Memory Address Space As its on-chip ROM, the H8/3048F has 128 kbytes of flash memory. The flash memory is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states.
Page 580 • Erase-program cycles Flash memory contents can be erased and reprogrammed up to 100 times. • On-board programming modes These modes can be used to program, erase, and verify flash memory contents. There are two modes: boot mode, and user programming mode. •...
Page 581: Block Diagram
18.4.4 Block Diagram Figure 18-7 shows a block diagram of the flash memory. Internal data bus (upper) Internal data bus (lower) Operating FLMCR Bus interface and control section mode H'00000 H'00001 EBR1 H'00002 H'00003 EBR2 H'00004 H'00005 On-chip flash memory (128 kbytes) H'1FFFC H'1FFFD...
Page 582: Input/Output Pins
18.4.5 Input/Output Pins Flash memory is controlled by the pins listed in table 18-9. Table 18-9 Flash Memory Pins Pin Name Abbreviation Input/Output Function Programming power Power supply Apply 12.0 V Mode 2 Input H8/3048F operating mode programming Mode 1 Input H8/3048F operating mode programming...
Page 583: Flash Memory Register Descriptions
18.5 Flash Memory Register Descriptions 18.5.1 Flash Memory Control Register The flash memory control register (FLMCR) is an eight-bit register that controls the flash memory operating modes. Transitions to program mode, erase mode, program-verify mode, and erase- verify mode are made by setting bits in this register. FLMCR is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to V .
Page 584 Bit 7—Programming Power (V ): Programming power bit (V ) detects V , and level is displayed as “1” or “0.” The permissible output currents for impressed high voltage VH are given in 21.3.1, “DC Characteristics.” The value of VH ranges from V + 2 V to 11.4 V.
Page 585 Bits 5 to 4—Reserved: Read-only bits, always read as 0. Bit 3—Erase-Verify Mode (EV) : Selects transition to or exit from erase-verify mode. Bit 3 Description Exit from erase-verify mode (Initial value) Transition to erase-verify mode Bit 2—Erase-Verify Mode (PV) : Selects transition to or exit from program-verify mode.
Page 586: Erase Block Register 1
18.5.2 Erase Block Register 1 Erase block register 1 (EBR1) is an eight-bit register that designates large flash-memory blocks for programming and erasure. EBR1 is initialized to H'00 by a reset, in the standby modes, when 12 V is applied to V while the V E bit is 0, and when 12 V is not applied to V .
Page 587: Erase Block Register 2
18.5.3 Erase Block Register 2 Erase block register 2 (EBR2) is an eight-bit register that designates small flash-memory blocks for programming and erasure. EBR2 is initialized to H'00 by a reset, in the standby modes, when 12 V is applied to V while the V E bit is 0, and when 12 V is not applied to V .
Page 588 Addresses H'00000 H'00000–H'03FFF 16 kbytes H'03FFF H'04000 H'04000–H'07FFF 16 kbytes H'07FFF H'08000 H'08000–H'0BFFF 16 kbytes H'0BFFF Large block H'0C000 H'0C000–H'0FFFF 16 kbytes area H'0FFFF (124 kbytes) H'10000 H'10000–H'13FFF 16 kbytes H'13FFF H'14000 H'14000–H'17FFF 16 kbytes H'17FFF H'18000 H'18000–H'1BFFF 16 kbytes H'1BFFF H'1C000 H'1C000-H'1EFFF...
Page 589: Ram Control Register (Ramcr)
18.5.4 RAM Control Register (RAMCR) The RAM control register (RAMCR) enables flash-memory updates to be emulated in RAM, and indicates flash memory errors. FLER — — — RAMS RAM2 RAM1 RAM0 Initial value — — — Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was being programmed or erased.
Page 590 Bits 6 to 4—Reserved: Read-only bits, always read as 1. Bit 3—RAM Select (RAMS): Is used with bits 2 to 0 to reassign an area to RAM (see table 18- 11). When bit 3 is set, all flash-memory blocks are protected from programming and erasing, regardless of the values of bits 2 to 0.
Page 591: On-Board Programming Modes
18.6 On-Board Programming Modes When an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. There are two on-board programming modes: boot mode, and user program mode. These modes are selected by inputs at the mode pins (MD to MD ) and V pin.
Page 592 Boot-Mode Execution Procedure: Figure 18-10 shows the boot-mode execution procedure. 1. Program the H8/3048F pins for boot mode, and start the Start H8/3048F from a reset. 2. Set the host's data format to 8 bits + 1 stop bit, select the Program H8/3048F pins for desired bit rate (2400, 4800 or 9600), and transmit H'00 boot mode, and resets.
Page 593 Automatic Alignment of SCI Bit Rate Start Stop This low period (9 bits) is measured (H'00 data) High for at least 1 bit Figure 18-11 Measurement of Low Period in Data Transmitted from Host When started in boot mode, the H8/3048F measures the low period in asynchronous SCI data transmitted from the host (figure 18-11).
Page 594 RAM Area Allocation in Boot Mode: In boot mode, the H'3F0 bytes from H'FEF10 to H'FF2FF in modes 5 and 7, and from H'FFEF10 to H'FFF2FF in mode 6 are reserved for use by the boot program. The user program is transferred into the area from H'FF300 to H'FFEFF, in modes 5 and 7, and from H'FFF300 to H'FFFEFF in mode 6 (H'C00 bytes).
Page 595 4. The RXD and TXD lines should be pulled up on-board. 5. Before branching to the user program (at address H'F300 in the RAM area), the H8/3048F terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in serial control register (SCR) to 0 in channel 1), but the auto-aligned bit rate remains set in bit rate register BRR1.
Page 596: User Program Mode
8. Regarding 12 V application to the V and MD pins, insure that peak overshoot does not exceed the maximum rating of 13 V. Also, be sure to connect bypass capacitors to the Vpp and MD pins* Notes: 1. Mode pin input must satisfy the mode programming setup time (t ) with respect to the reset release timing.
Page 597 The flash memory cannot be read while being programmed or erased, so the update program must either be stored in external memory, or transferred temporarily to the RAM area and executed in RAM. User Program Mode Execution Procedure: Figure 18-13 shows the procedure for user program mode execution in RAM.
Page 598: Programming And Erasing Flash Memory
18.7 Programming and Erasing Flash Memory The H8/3048F’s on-chip flash memory is programmed and erased by software, using the CPU. The flash memory operating modes and state transition diagram are shown in figure 18-14. Program/erase modes comprise program mode, erase mode, program-verify mode, erase-verify mode, and prewrite-verify mode.
Page 599: Program Mode
18.7.1 Program Mode To write data into the flash memory, follow the programming algorithm shown in figure 18-15. This programming algorithm can write data without subjecting the device to voltage stress or impairing the reliability of programmed data. To program data, first set the V E bit in FLMCR, wait 5 to 10 µs, then designate the blocks to be programmed by erase block registers 1 and 2 (EBR1, EBR2), and write the data to the address to be programmed, as in writing to RAM.
Page 600: Programming Flowchart And Sample Program
18.7.3 Programming Flowchart and Sample Program Flowchart for Programming One Byte Start n = 1 Set V E bit E bit = 1 in FLMCR) Wait (z) µs Set erase block register (set bit of block to be programmed to 1) Write data to flash memory (flash memory latches write address and data)
Page 601 Sample Program for Programming One Byte: This program uses the following registers. Program-verify fail counter Program-verify timing loop counter ER2: Stores the address to be programmed as long word data. Valid addresses are H'00000000 to H'0001FFFF. R3H: Stores data to be programmed as byte data Sets and clears TCSR and FLMCR Stores the initial program loop counter value Clears FLMCR...
Page 602: Erase Mode
Compare programmed data with read data CMP.B R3H, PVOK Program-verify decision PVNG: MOV.B #40, MOV.B R5H, @FLMCR:8 ; Clear PV bit Program-verify executed 6 times? CMP.B #06, NGEND If program-verify executed 6 times, branch to NGEND Program-verify fail count + 1 → R0L INC.B Double program loop counter value SHLL.W...
Page 603: Erase-Verify Mode
18.7.5 Erase-Verify Mode In program-verify mode, after data has been erased, it is read to check that it has been erased correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0), select erase- verify mode (set the EV bit to 1), and wait 4 µs. Before reading data in erase-verify mode, write H'FF dummy data to the address to be read.
Page 604: Erasing Flowchart And Sample Program
18.7.6 Erasing Flowchart and Sample Program Flowchart for Erasing One Block Start Write 0 data in all addresses Notes: 1. Program all addresses to be to be erased (prewrite) erased by following the prewrite flowchart. n = 1 2. Set the watchdog timer overflow interval to the value indicated in bit = 1 in FLMCR) table 18-15.
Page 605 Prewrite Flowchart Start Address = top address bit = 1 in FLMCR) Wait (z) µs Set erase block register (set bit of block to be erased to 1) n = 1 Address + 1 → address Wait initial value setting x = 15 µs Notes: 1.
Page 606 Sample Program for Erasing One Block: This program uses the following registers. Prewrite-verify and erase-verify fail counter ER1: Stores address used in prewrite ER2: Stores address used in prewrite and erase-verify ER3: Stores address used in erase-verify ER4: Timing loop counter Sets appropriate registers Sets appropriate registers The values of #a, #c, #d, #e, #f, #g, and #h, in the program depend on the clock frequency.
Page 607 Wait LOOPR2: DEC.W LOOPR2 Read data = H'00? MOV.B @ER1, PWVFOK If read data = H'00, branch to PWVFOK CMP.B #05, Prewrite-verify executed 6 times? If prewrite-verify executed 6 times, branch ABEND1 to ABEND1 Double prewrite loop counter value SHLL.W Prewrite-verify fail count + 1 →...
Page 608 LOOPDW: DEC.W LOOPDW Wait Read MOV.B @ER3+, CMP.B #FF, Read data = H’FF? If read data ≠ H’FF, branch to RERASE RERASE Last address in block? CMP.L ER2, EVR2 If not last address in block, erase-verify next address OKEND, Branch to OKEND RERASE: MOV.W #4000, Clear EV bit...
Page 609 Flowchart for Erasing Multiple Blocks Notes: 1. Program all addresses to be erased by Start following the prewrite flowchart. Write 0 data to all addresses to be 2. Set the watchdog timer overflow interval to erased (prewrite) the value indicated in table 18-15. n = 1 3.
Page 610 Sample Program for Erasing Multiple Blocks: This program uses the following registers. R0, R6: Specifies blocks to be erased (set as explained below) R1H: Prewrite-verify fail counter R1L: Used to test bits 0 to 15 of R0 ER2: Specifies address where address used in prewrite and erase-verify is stored ER3: Stores address used in prewrite and erase-verify ER4:...
Page 611 FLMCR: .EQU FFFF40 EBR1: .EQU FFFF42 EBR2: .EQU FFFF43 TCSR: .EQU FFFFA8 Set R0 value START: MOV.W #FFFF, Select blocks to be erased (R6: EBR1/EBR2) R0: EBR1/EBR2 MOV.W SUB.W R1L: used to test R1-th bit in R0 #RAMSTR is starting destination address to which program is transferred in RAM Set #RAMSTR to even number Starting transfer destination address MOV.L...
Page 612 Program LOOPR1: DEC.W LOOPR1 Clear P bit MOV.B R5L, @FLMCR:8 ; MOV.W #A500, MOV.W @TCSR:16 ; Stop watchdog timer Prewrite-verify loop counter MOV.W LOOPR2: DEC.W LOOPR2 MOV.B @ER3, Read data = #'00? If read data = #'00, branch to PWVFOK PWVFOK PWVFNG: CMP.B #06,...
Page 613 Execute erase-verify EVR: MOV.W R0: EBR1/EBR2 R1: used to test R1-th bit in R0 SUB.W #RAMSTR is starting destination address to which program is transferred in RAM Starting transfer destination address (RAM) MOV.L #RAMSTR:32, ER2 #RAMSTR + #ERVADR → ER2 ADD.L #ERVADR:32, ER2 ER2: address of data area used in RAM...
Page 614 HANTEI: MOV.W #4000, MOV.B R5H, @FLMCR:8 ; Clear EV bit Clear bit of erased block to 0 MOV.W @EBR1:16 ; EOWARI If EBR1/EBR2 is all 0, erasing ended normally E6 = 025A? (erase-verify fail count = 602?) CMP.W #025A, If E6 = 025A, branch to ABEND2 ABEND2 Erase-verify fail count + 1 →...
Page 615 Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings: The values of a to h in the programs depend on the clock frequency. Table 18-14 indicates the values for 10 MHz. Values for other frequencies can be calculated as shown below, but use the settings in table 18-15 for the value off.
Page 616: Prewrite-Verify Mode
18.7.7 Prewrite-Verify Mode Prewrite-verify mode is a verify mode used after writing 0 to all bits to equalize their threshold voltages before erasure. To program all bits, write H'00 in accordance with the algorithm shown in figure 18-17. Use this procedure to set all data in the flash memory to H'00 after programming.
Page 617 Hardware Protection: Suspends or disables the programming and erasing of flash memory, and resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2). The error-protect function permits the P and E bits to be set, but prevents transitions to program mode and erase mode.
Page 618 The error-protect state can be cleared only by a reset or entry to hardware standby mode. Note: * It is possible to write to these registers. Note that a transition to software standby mode initializes these registers. Memory read or verify mode RES = 0 or STBY = 0 or software standby RD VF PR ER...
Page 619: Nmi Input Masking
programming or erasing, or it may contain data that has been insufficiently programmed or erased because of the suspension of these operations. Boot mode should be used to recover to a normal state. If the memory contains overerased memory cells, boot mode may not operate correctly. This is because the H8/3048F’s built-in boot program is located in part of flash memory, and will not read correctly if memory cells have been overerased.
Page 620: Flash Memory Emulation By Ram
18.8 Flash Memory Emulation by RAM Erasing and programming flash memory takes time, which can make it difficult to tune parameters and other data in real time. If necessary, real-time updates of flash memory can be emulated by overlapping the small-block flash-memory area with part of the RAM (H'FFF000 to H'FFF1FF). This RAM reassignment is performed using bits 3 to 0 of the RAM control register (RAMCR).
Page 621 Example of Emulation of Real-Time Flash-Memory Update H'01F000 Procedure 1. Set the RAME bit to 1 in SYSCR to enable the on-chip RAM. Flash memory address space 2. Overlap part of RAM (H'FFF000 to H'FFF1FF) onto the area requiring real-time update (SB5). (Set RAMCR bits 3 to 0 to 1101.) Overlapped by RAM H'01F9FF...
Page 622: Flash Memory Prom Mode
18.9 Flash Memory PROM Mode 18.9.1 PROM Mode Setting The on-chip flash memory of the H8/3048F can be programmed and erased not only in the on- board programming modes but also in PROM mode, using a general-purpose PROM programmer. Table 18-17 indicates how to select PROM mode. Be sure to use the indicated socket adapter in PROM mode.
Page 623: Socket Adapter And Memory Map
18.9.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a special 100-pin/32-pin socket adapter to the PROM programmer. Table 18-18 gives ordering information for the socket adapter. Figure 18-21 shows a memory map in PROM mode. Figure 18-22 shows the socket adapter pin interconnections.
Page 624 H8/3048F Pin No. Socket Adapter HN28F101 (32 Pins) Pin Name FP-100B, TFP-100B Pin Name Pin No. RESO 53, 54, 89 , P5 , P8 62, 71 STBY, HWR 73 to 75 , MD , MD Legend 87, 88, 14 , P8 , P9 Programming 76, 77...
Page 625: Operation In Prom Mode
18.9.3 Operation in PROM Mode The program/erase/verify specifications in PROM mode are the same as for the standard HN28F101 flash memory. Table 18-20 indicates how to select the various operating modes. The H8/3048F does not have a device recognition code, so the programmer cannot read the device name automatically.
Page 626 Table 18-21 PROM Mode Commands 1st Cycle 2nd Cycle Command Cycles Mode Address Data Mode Address Data Memory read Write H'00 Read Dout Erase setup/erase Write H'20 Write H'20 Erase-verify Write H'A0 Read Auto-erase setup/ Write H'30 Write H'30 auto-erase Program setup/ Write H'40...
Page 627 High-Speed, High-Reliability Programming: Unused areas of the H8/3048F flash memory contain H'FF data (initial value). The H8/3048F flash memory uses a high-speed, high-reliability programming procedure. This procedure provides enhanced programming speed without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. Figure 18-23 shows the basic high-speed, high-reliability programming flowchart.
Page 628 High-Speed, High-Reliability Erasing: The H8/3048F flash memory uses a high-speed, high- reliability erasing procedure. This procedure provides enhanced erasing speed without subjecting the device to voltage stress and without sacrificing data reliability . Figure 18-24 shows the basic high-speed, high-reliability erasing flowchart. Tables 18-22 and 18-23 list the electrical characteristics during programming.
Page 629 Table 18-22 DC Characteristics in PROM Mode (Conditions: V = 5.0 V ±10%, V = 12.0 V ±0.6 V, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Test Conditions Input high to I/O — + 0.3 voltage to A OE, CE, WE Input low...
Page 630 Table 18-23 AC Characteristics in PROM Mode (Conditions: V = 5.0 V ± 10%, V = 12.0 V ± 0.6 V, V = 0 V, T = 25°C ± 5°C) Item Symbol Unit Test Conditions Command write cycle — — Figure 18-25 Figure 18-26 Address setup time...
Page 631 Auto-erase setup Auto-erase and status polling 5.0 V 12 V 5.0 V Address OEPS OEWS Command Command Status polling I/O to I/O Command Command Figure 18-25 Auto-Erase Timing Program setup Program Program-verify 5.0 V 12 V 5.0 V Address Valid address OERS OEWS Data...
Page 632 Erase setup Erase Erase-verify 5.0 V 12 V 5.0 V Address Valid address OEWS OERS Command Command Command Valid data to I/O Note: Erase-verify data output values may be intermediate between 1 and 0 if erasing is insufficient. Figure 18-27 Erase Timing...
Page 633: Flash Memory Programming And Erasing Precautions
The programming voltage (V ) of the flash memory is 12.0 V. If the PROM programmer is set to Hitachi HN28F101 specifications, V will be 12.0 V. Applied voltages in excess of the rating can permanently damage the device. Insure, in particular, that peak overshoot at the Vpp and MD2 pins does not exceed the maximum rating of 13 V.
Page 634 (b) The V bit in the flash memory control register (FLMCR) is set or cleared when the V bit in FLMCR is set or cleared while a voltage of 12.0 ± 0.6 V is being applied to the V pin. After the V E bit is set, it becomes possible to write the erase block registers (EBR1 and EBR2) and the EV, PV, E, and P bits in FLMCR.
Page 635 Programming/ erasing possible ø min 0 µs tosc1 2.7 to 5.5 V 12±0.6 V 0 to 0 to Vcc V Vcc V 0 to Vcc V 0 to Vcc V to 0 VppE VppE cleared E bit Period during which flash memory access is prohibited Period during which flash memory can be rewritten (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 636 Programming/ Programming/ Programming/ Programming/ erasing erasing erasing erasing possible possible possible possible ø tosc1 2.7 to 5.5 V 12±0.6 V 0 to min 0 µs Vcc V min 10 ø 12±0.6 V 0 to Vcc V to 0 min 0µs VppE Clear cleared...
Page 637 (5) Do not apply 12 V to the V pin during normal operation. To prevent microcontroller errors caused by accidental programming or erasing, apply 12 V to V only when the flash memory is programmed or erased, or when flash memory is emulated by RAM. While 12 V is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing.
Page 638 (8) Notes concerning mounting board development—handling of V and mode MD2 pins 1. The standard 12 V high voltage is applied to the V and mode MD2 pins when erasing or programming flash memory. The voltage at these pins also includes overshoot and noise, and the following points should be noted to ensure that the 13 V maximum rated voltage is not exceeded.
Page 639 2. 12 V is applied to the V and mode MD2 pins when programming or erasing flash memory. When these pins are pulled up to the V line in normal operation, diodes should be inserted to prevent reverse current from flowing to the V line when 12 V is applied.
Page 640 (9) Do not set or clear the VppE bit during execution of a program in flash memory. Flash memory data cannot be read normally when the VppE bit is set or cleared. After the VppE bit is cleared, flash memory data can be rewritten after waiting for the elapse of the Vpp enable setup time (tVPS: 5 10 [??] µs), but flash memory cannot be accessed for purposes other than verification (verification during programming, erasing, or prewriting).
Page 641 18.11 Notes on Ordering Masked ROM Version Chip When ordering the H8/3048 Series chips with a masked ROM, note the following. • When ordering through an EPROM, use a 128-kbyte one. • Fill all the unused addresses with H'FF as shown in figure 18-33 to make the ROM data size 128 kbytes for all H8/3048 Series chips, which incorporate different sizes of ROM.
Page 642: Clock Pulse Generator
Section 19 Clock Pulse Generator 19.1 Overview The H8/3048 Series has a built-in clock pulse generator (CPG) that generates the system clock (ø) and other internal clock signals (ø/2 to ø/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (ø). The system clock is output at the ø pin furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules.
Page 643: Oscillator Circuit
If the chip is to be operated at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of less than 2 MHz cannot be used.) * HD6473048, HD6433048, HD6433047, HD6433045, HD6433044 Crystal Resonator: Figure 19-3 shows an equivalent circuit of the crystal resonator. The crystal...
Page 644 XTAL EXTAL AT-cut parallel-resonance type Figure 19-3 Crystal Resonator Equivalent Circuit Table 19-2 Crystal Resonator Parameters Frequency (MHz) Rs max (Ω) Co (pF) 7 pF max Use a crystal resonator with a frequency equal to the system clock frequency (ø). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from...
Page 645: External Clock Input
19.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 19-5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF in configuration a, use configuration b instead and hold the clock high in standby mode.
Page 646 External Clock: The external clock frequency should be equal to the system clock frequency (ø) when not divided by the on-chip frequency divider. Table 19-3, figures 19-6 and 19-7 indicate the clock timing. When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit.
Page 647 × 0.7 EXTAL × 0.5 0.3 V Figure 19-6 External Clock Input Timing 2.7 V STBY EXTAL ø (internal or external) DEXT of RES (t Note: * t includes 10 t DEXT RESW Figure 19-7 External Clock Output Settling Delay Timing...
Page 648: Duty Adjustment Circuit
19.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the signal that becomes the system clock. 19.4 Prescalers The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096). 19.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (ø).
Page 649: Usage Notes
Bits 7 to 2—Reserved: Read-only bits, always read as 1. Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as follows. Bit 1 Bit 0 DIV1 DIV0 Frequency Division Ratio (Initial value) 19.5.3 Usage Notes The DIVCR setting changes the ø...
Page 650: Power-Down State
Section 20 Power-Down State 20.1 Overview The H8/3048 Series has a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: •...
Page 652: Register Configuration
20.2 Register Configuration The H8/3048 Series has a system control register (SYSCR) that controls the power-down state, and a module standby control register (MSTCR) that controls the module standby function. Table 20-2 summarizes these registers. Table 20-2 Control Register Address* Name Abbreviation Initial Value...
Page 653 Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description SLEEP instruction causes transition to sleep mode...
Page 654: Module Standby Control Register (Mstcr)
20.2.2 Module Standby Control Register (MSTCR) MSTCR is an 8-bit readable/writable register that controls output of the system clock (ø). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the ITU, SCI0, SCI1, DMAC, refresh controller, and A/D converter modules.
Page 655 Bit 4—Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby. Bit 4 MSTOP4 Description SCI0 operates normally (Initial value) SCI0 is in standby state Bit 3—Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby. Bit 3 MSTOP3 Description SCI1 operates normally (Initial value)
Page 656: Sleep Mode
20.3 Sleep Mode 20.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA controller (DMAC), refresh controller, and on-chip supporting modules do not halt in sleep mode.
Page 657: Software Standby Mode
20.4 Software Standby Mode 20.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt.
Page 658: Selection Of Waiting Time For Exit From Software Standby Mode
20.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms.
Page 659: Sample Application Of Software Standby Mode
20.4.4 Sample Application of Software Standby Mode Figure 20-1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 660: Hardware Standby Mode
20.5 Hardware Standby Mode 20.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, refresh controller, and on-chip supporting modules. All modules are reset except the on-chip RAM.
Page 661: Module Standby Function
20.6 Module Standby Function 20.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0, SCI1, DMAC, refresh controller, and A/D converter) independently of the power-down state. This standby function is controlled by bits MSTOP5 to MSTOP0 in MSTCR. When one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle.
Page 662: System Clock Output Disabling Function
20.7 System Clock Output Disabling Function Output of the system clock (ø) can be controlled by the PSTOP bit in MSTCR. When the PSTOP bit is set to 1, output of the system clock halts and the ø pin is placed in the high-impedance state. Figure 20-3 shows the timing of the stopping and starting of system clock output.
Page 663: Electrical Characteristics
Table 21-1 lists the absolute maximum ratings. Table 21-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Programming voltage HD6473048 –0.3 to +13.5 HD64F3048 –0.3 to +13.0 Input voltage –0.3 to V + 0.3 (except for MD port 7...
Page 664: Electrical Characteristics Of Masked Rom And Prom Versions
21.2 Electrical Characteristics of Masked ROM and PROM Versions 21.2.1 DC Characteristics Table 21-2 lists the DC characteristics. Table 21-3 lists the permissible output currents. Table 21-2 DC Characteristics Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V*, T...
Page 665: Dc Characteristics
Table 21-2 DC Characteristics (cont) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 666 Table 21-2 DC Characteristics (cont) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 667 Table 21-2 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 668 Table 21-2 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 669 Table 21-2 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 670 Table 21-3 Permissible Output Currents Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 671 H8/3048 Series 2 kΩ Port Darlington pair Figure 21-1 Darlington Pair Drive Circuit (Example) H8/3048 Series Ports 1, 2, 5, 600 Ω and B Figure 21-2 LED Drive Circuit (Example)
Page 672: Ac Characteristics
21.2.2 AC Characteristics Bus timing parameters are listed in table 21-4. Refresh controller bus timing parameters are listed in table 21-5. Control signal timing parameters are listed in table 21-6. Timing parameters of the on-chip supporting modules are listed in table 21-7. Table 21-4 Bus Timing (1) Condition A: V = 2.7 V to 5.5 V, AV...
Page 673 Table 21-4 Bus Timing (cont) Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 674 Note: At 8 MHz, the times below depend as indicated on the clock cycle time. = 1.5 × t = 1.0 × t – 68 (ns) – 40 (ns) ACC1 WSW1 = 2.5 × t = 1.5 × t – 73 (ns) –...
Page 675 Table 21-5 Refresh Controller Bus Timing Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 676 Note: At 8 MHz, the times below depend as indicated on the clock cycle time. = 0.5 × t = 1.0 × t – 38 (ns) – 75 (ns) = 2.0 × t = 0.5 × t – 90 (ns) –...
Page 677 Table 21-6 Control Signal Timing Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 678 Table 21-7 Timing of On-Chip Supporting Modules Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 679 Table 21-7 Timing of On-Chip Supporting Modules (cont) Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 680: A/D Conversion Characteristics
21.2.3 A/D Conversion Characteristics Table 21-8 lists the A/D conversion characteristics. Table 21-8 A/D Converter Characteristics Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø...
Page 681: D/A Conversion Characteristics
21.2.4 D/A Conversion Characteristics Table 21-9 lists the D/A conversion characteristics. Table 21-9 D/A Converter Characteristics Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø...
Page 682: Electrical Characteristics Of Flash Memory Version
21.3 Electrical Characteristics of Flash Memory Version 21.3.1 DC Characteristics Table 21-10 lists the DC characteristics. Table 21-11 lists the permissible output currents. Table 21-10 DC Characteristics Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V*, T...
Page 683: Dc Characteristics
Table 21-10 DC Characteristics (cont) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 684 Table 21-10 DC Characteristics (cont) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 685 Table 21-10 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 686 Table 21-10 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 687 Table 21-10 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 688 Table 21-10 DC Characteristics (cont) —Preliminary— Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 689 Table 21-11 Permissible Output Currents Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 690 H8/3048 Series 2 kΩ Port Darlington pair Figure 21-4 Darlington Pair Drive Circuit (Example) H8/3048 Series Ports 1, 2, 5, 600 Ω and B Figure 21-5 LED Drive Circuit (Example)
Page 691: Ac Characteristics
21.3.2 AC Characteristics Bus timing parameters are listed in table 21-12. Refresh controller bus timing parameters are listed in table 21-13. Control signal timing parameters are listed in table 21-14. Timing parameters of the on-chip supporting modules are listed in table 21-15. Table 21-12 Bus Timing (1) Condition A: V = 2.7 V to 5.5 V, AV...
Page 692 Table 21-12 Bus Timing (cont) Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 693 Table 21-13 Refresh Controller Bus Timing Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 694 Table 21-14 Control Signal Timing Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 695 Table 21-15 Timing of On-Chip Supporting Modules Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 696 Table 21-15 Timing of On-Chip Supporting Modules (cont) Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 1 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 697: A/D Conversion Characteristics
21.3.3 A/D Conversion Characteristics Table 21-16 lists the A/D conversion characteristics. Table 21-16 A/D Converter Characteristics Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø...
Page 698: D/A Conversion Characteristics
21.3.4 D/A Conversion Characteristics Table 21-17 lists the D/A conversion characteristics. Table 21-17 D/A Converter Characteristics Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø...
Page 699: Flash Memory Characteristics
21.3.5 Flash Memory Characteristics Table 21-18 lists the flash memory characteristics. Table 21-18 Flash Memory Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, V = 12 V ±...
Page 700: Operational Timing
21.4 Operational Timing This section shows timing diagrams. 21.4.1 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 21-7 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 21-8 shows the timing of the external three-state access cycle.
Page 701 ø to A CS to CS ACC3 ACC3 (read) ACC1 to D (read) HWR, LWR (write) WSW1 WDS1 to D (write) Figure 21-7 Basic Bus Cycle: Two-State Access...
Page 702 ø to A ACC4 ACC4 RD (read) ACC2 to D (read) WSW2 HWR, LWR (write) WDS2 to D (write) Figure 21-8 Basic Bus Cycle: Three-State Access...
Page 703 ø to A RD (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 21-9 Basic Bus Cycle: Three-State Access with One Wait State...
Page 704: Refresh Controller Bus Timing
21.4.2 Refresh Controller Bus Timing Refresh controller bus timing is shown as follows: • DRAM bus timing Figures 21-10 to 21-15 show the DRAM bus timing in each operating mode. • PSRAM bus timing Figures 21-16 and 21-17 show the pseudo-static RAM bus timing in each operating mode. ø...
Page 705 ø to A RAD3 CS3 (RAS) RAD2 RD (CAS) HWR (UW), LWR (LW) RAD2 RAD3 RFSH Figure 21-11 DRAM Bus Timing (Refresh Cycle): Three-State Access — 2WE Mode — ø CS (RAS) RD (CAS) RFSH Figure 21-12 DRAM Bus Timing (Self-Refresh Mode) —...
Page 706 ø to A RAD3 RAD1 CS (RAS HWR (UCAS), LWR (LCAS) RD (WE) (read) RD (WE) (write) RFSH to D (read) WDS3 to D (write) Figure 21-13 DRAM Bus Timing (Read/Write): Three-State Access — 2CAS Mode —...
Page 707 ø to A RAD3 CS (RAS) RAD2 HWR (UCAS), LWR (LCAS) RD (WE) RAD2 RAD3 RFSH Figure 21-14 DRAM Bus Timing (Refresh Cycle): Three-State Access — 2CAS Mode — ø CS (RAS) UCAS LCAS) RFSH Figure 21-15 DRAM Bus Timing (Self-Refresh Mode) —...
Page 708 ø to A RAD1 RAD3 RD (read) to D (read) HWR, LWR (write) WDS2 to D (write) RFSH Figure 21-16 PSRAM Bus Timing (Read/Write): Three-State Access ø to A , HWR, LWR, RD RAD2 RAD3 RFSH Figure 21-17 PSRAM Bus Timing (Refresh Cycle): Three-State Access...
Page 709: Control Signal Timing
21.4.3 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 21-18 shows the reset input timing. • Reset output timing Figure 21-19 shows the reset output timing. • Interrupt input timing Figure 21-20 shows the input timing for NMI and IRQ to IRQ •...
Page 710 ø NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0 to 5) NMIW (j = 0 to 2) Figure 21-20 Interrupt Input Timing ø BRQS BRQS BREQ BACD2 BACD1 BACK to A AS, RD, HWR, LWR Figure 21-21 Bus-Release Mode Timing...
Page 711: Clock Timing
21.4.4 Clock Timing Clock timing is shown as follows: • Oscillator settling timing Figure 21-22 shows the oscillator settling timing. ø STBY OSC1 OSC1 Figure 21-22 Oscillator Settling Timing 21.4.5 TPC and I/O Port Timing Figure 21-23 shows the TPC and I/O port timing. ø...
Page 712: Itu Timing
21.4.6 ITU Timing ITU timing is shown as follows: • ITU input/output timing Figure 21-24 shows the ITU input/output timing. • ITU external clock input timing Figure 21-25 shows the ITU external clock input timing. ø TOCD Output compare TICS Input capture Notes: 1.
Page 713: Sci Input/Output Timing
21.4.7 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 21-26 shows the SCK input clock timing. • SCI input/output timing (synchronous mode) Figure 21-27 shows the SCI input/output timing in synchronous mode. SCKW SCKr SCKf SCK0, SCK1...
Page 714: Dmac Timing
21.4.8 DMAC Timing DMAC timing is shown as follows. TEND output timing for 2 state access • DMAC Figure 21-28 shows the DMAC TEND output timing for 2 state access. DMAC TEND output timing for 3 state access • Figure 21-29 shows the DMAC TEND output timing for 3 state access. DMAC DREQ input timing •...
Page 715 ø DRQS DRQH DREQ Figure 21-30 DMAC DREQ Input Timing...
Page 716: Appendix A Instruction Set
Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
Page 717 Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes...
Page 718: Data Transfer Instructions
Table A-1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — Rs8 → Rd8 MOV.B Rs, Rd —...
Page 719 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W @aa:24 → Rd16 MOV.W @aa:24, Rd — — 0 — W Rs16 → @ERd MOV.W Rs, @ERd — — 0 —...
Page 720: Arithmetic Instructions
Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W SP–2 → SP PUSH.W Rn 2 — — 0 — Rn16 → @SP SP–4 → SP PUSH.L ERn 4 —...
Page 721 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32 INC.L #1, ERd — — — ERd32+2 → ERd32 INC.L #2, ERd — — — DAA Rd Rd8 decimal adjust —...
Page 722 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W ERd32 ÷ Rs16 →ERd32 DIVXU. W Rs, ERd — — (6) (7) — — (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷...
Page 723: Logic Instructions
Table A-1 Instruction Set (cont) 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — 0 — Rd8∧Rs8 → Rd8 AND.B Rs, Rd —...
Page 724: Shift Instructions
Table A-1 Instruction Set (cont) 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd —...
Page 725: Bit Manipulation Instructions
Table A-1 Instruction Set (cont) 5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 726 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 —...
Page 727: Branching Instructions
Table A-1 Instruction Set (cont) 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Branch Mnemonic Operation Condition H N Z BRA d:8 (BT d:8) — Always — — — — — — If condition is true then BRA d:16 (BT d:16) —...
Page 728 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Branch Mnemonic Operation Condition H N Z Z ∨ (N⊕V) = 1 BLE d:8 — If condition — — — — — — is true BLE d:16 —...
Page 729: System Control Instructions
Table A-1 Instruction Set (cont) 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z — PC → @–SP TRAPA #x:2 1 — — — — — CCR → @–SP <vector>...
Page 730 Table A-1 Instruction Set (cont) 8. Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z — if R4L ≠ 0 then EEPMOV. B 4 — — — — — — repeat @R5 →...
Page 731: Operation Code Map
A.2 Operation Code Map...
Page 734: Number Of States Required For Execution
A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A-4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-3 indicates the number of states required per cycle according to the bus size.
Page 735 Table A-3 Number of States per Cycle Access Conditions External Device On-Chip Sup- porting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read Stack operation Byte data access...
Page 736 Table A-4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd ADDX...
Page 737 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16...
Page 738 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd...
Page 739 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd...
Page 740 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd 2 MOV.B @(d:24, ERs), Rd 4 MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd...
Page 741 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOVFPE MOVFPE @aa:16, Rd MOVTPE MOVTPE Rs, @aa:16 MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd...
Page 742 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic Normal* Advanced 2 SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd...
Page 743: Appendix B Internal I/O Register
Appendix B Internal I/O Register B.1 Addresses Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'1C H'1D H'1E H'1F H'20 MAR0AR DMAC channel 0A H'21 MAR0AE...
Page 744 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'30 MAR1AR DMAC channel 1A H'31 MAR1AE H'32 MAR1AH H'33 MAR1AL H'34 ETCR1AH 8...
Page 745 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'4C — — — — — — — — — —...
Page 746 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'70 TIER1 — — — — — OVIE IMIEB IMIEA ITU channel 1 H'71 TSR1...
Page 747 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'94 TIER4 — — — — — OVIE IMIEB IMIEA ITU channel 4 H'95 TSR4...
Page 748 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'B0 C/A/GM CHR STOP CKS1 CKS0 SCI channel 0 H'B1 H'B2 MPIE TEIE...
Page 749 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'D4 PBDDR DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB...
Page 750 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FA — — — — — — — — — H'FB —...
Page 751: Function
B.2 Function Register Register Address to which Name of on-chip acronym name the register is mapped supporting module TSTR Timer Start Register H'60 ITU (all channels) numbers Initial bit — — — STR4 STR3 STR2 STR1 STR0 values Initial value Names of the Read/Write —...
Page 752 MAR0A R/E/H/L—Memory Address Register 0A R/E/H/L H'20, H'21, DMAC0 H'22, H'23 Undetermined Initial value Read/Write — — — — — — — — MAR0AR MAR0AE Initial value Undetermined Undetermined Read/Write MAR0AH MAR0AL Source or destination address...
Page 753 ETCR0A H/L—Execute Transfer Count Register 0A H/L H'24, H'25 DMAC0 • Short address mode I/O mode and idle mode Initial value Undetermined Read/Write Transfer counter Repeat mode Initial value Undetermined Read/Write ETCR0AH Transfer counter Initial value Undetermined Read/Write ETCR0AL Initial count...
Page 754 ETCR0A H/L—Execute Transfer Count Register 0A H/L H'24, H'25 DMAC0 (cont) • Full address mode Normal mode Initial value Undetermined Read/Write Transfer counter Block transfer mode Initial value Undetermined Read/Write ETCR0AH Block size counter Initial value Undetermined Read/Write ETCR0AL Initial block size...
Page 755 IOAR0A—I/O Address Register 0A H'26 DMAC0 Initial value Undetermined Read/Write Short address mode: source or destination address Full address mode: not used...
Page 756 DTCR0A—Data Transfer Control Register 0A H'27 DMAC0 • Short address mode DTSZ DTID DTIE DTS0 DTS2 DTS1 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 Data Transfer Activation Source Compare match/input capture A interrupt from ITU channel 0 Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2 Compare match/input capture A interrupt from ITU channel 3...
Page 757 DTCR0A—Data Transfer Control Register 0A H'27 DMAC0 (cont) • Full address mode DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Initial value Read/Write Data transfer select 0A 0 Normal mode 1 Block transfer mode Data transfer select 2A and 1A Set both bits to 1 Data transfer interrupt enable 0 Interrupt request by DTE bit is disabled 1 Interrupt request by DTE bit is enabled...
Page 758 MAR0B R/E/H/L—Memory Address Register 0B R/E/H/L H'28, H'29, DMAC0 H'2A, H'2B Initial value Undetermined Read/Write — — — — — — — — MAR0BR MAR0BE Undetermined Undetermined Initial value Read/Write MAR0BH MAR0BL Source or destination address...
Page 759 ETCR0B H/L—Execute Transfer Count Register 0B H/L H'2C, H'2D DMAC0 • Short address mode I/O mode and idle mode Initial value Undetermined Read/Write Transfer counter Repeat mode Initial value Undetermined Read/Write ETCR0BH Transfer counter Initial value Undetermined Read/Write ETCR0BL Initial count...
Page 760 ETCR0B H/L—Execute Transfer Count Register 0B H/L H'2C, H'2D DMAC0 (cont) • Full address mode Normal mode Initial value Undetermined Read/Write Not used Block transfer mode Initial value Undetermined Read/Write Block transfer counter IOAR0B—I/O Address Register 0B H'2E DMAC0 Initial value Undetermined Read/Write Short address mode:...
Page 761 DTCR0B—Data Transfer Control Register 0B H'2F DMAC0 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 Data Transfer Activation Source Compare match/input capture A interrupt from ITU channel 0 Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2 Compare match/input capture A interrupt from ITU channel 3...
Page 762 DTCR0B—Data Transfer Control Register 0B H'2F DMAC0 cont • Full address mode DTME — DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Data transfer select 2B to 0B Bit 2 Bit 1 Bit 0 Data Transfer Activation Source DTS2B DTS1B DTS0B Normal Mode Block Transfer Mode...
Page 763 MAR1A R/E/H/L—Memory Address Register 1A R/E/H/L H'30, H'31, DMAC1 H'32, H'33 Initial value Undetermined — — — — — — — — Read/Write MAR1AR MAR1AE Initial value Undetermined Undetermined Read/Write MAR1AH MAR1AL Note: Bit functions are the same as for DMAC0.
Page 764 ETCR1A H/L—Execute Transfer Count Register 1A H/L H'34, H'35 DMAC1 Initial value Undetermined Read/Write Initial value Undetermined Read/Write ETCR1AH Initial value Undetermined Read/Write ETCR1AL Note: Bit functions are the same as for DMAC0. IOAR1A—I/O Address Register 1A H'36 DMAC1 Initial value Undetermined Read/Write Note: Bit functions are the same as for DMAC0.
Page 765 DTCR1A—Data Transfer Control Register 1A H'37 DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write • Full address mode DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Initial value Read/Write Note: Bit functions are the same as for DMAC0. MAR1B R/E/H/L—Memory Address Register 1B R/E/H/L H'38, H'39, DMAC1...
Page 766 ETCR1B H/L—Execute Transfer Count Register 1B H/L H'3C, H'3D DMAC1 Initial value Undetermined Read/Write Initial value Undetermined Read/Write ETCR1BH Initial value Undetermined Read/Write ETCR1BL Note: Bit functions are the same as for DMAC0. IOAR1B—I/O Address Register 1B H'3E DMAC1 Initial value Undetermined Read/Write Note: Bit functions are the same as for DMAC0.
Page 767 DTCR1B—Data Transfer Control Register 1B H'3F DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write • Full address mode DTME — DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Note: Bit functions are the same as for DMAC0.
Page 768 FLMCR—Flash Memory Control Register H'40 Flash memory — — Initial value — — Program mode Exit from program mode (Initial value) Transition to program mode Erase mode Exit from erase mode (Initial value) Transition to erase mode Program-verify mode Exit from program-verify mode (Initial value) Transition to program-verify mode Erase-verify mode...
Page 769 EBR1—Erase Block Register 1 H'42 Flash memory Initial value R/W * Large block 7 to 0 Block LB7 to LB0 is not selected (Initial value) Block LB7 to LB0 is selected Note: * The initial value is H'00 in modes 5, 6 and 7 (on-chip flash memory enabled). In modes 1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is always read as H'FF.
Page 770 RAMCR—RAM Control Register H'48 Flash memory FLER — — — RAMS RAM2 RAM1 RAM0 Initial value — — — RAM select, RAM 2 to RAM 0 Bit 3 Bit 2 Bit 1 Bit 0 RAMS RAM 2 RAM 1 RAM 0 RAM Area H'FFF000 to H'FFF1FF H'01F000 to H'01F1FF...
Page 771 DASTCR—D/A Standby Control Register H'5C System control — — — — — — — DASTE Initial value Read/Write — — — — — — — D/A standby enable 0 D/A output is disabled in software standby mode 1 D/A output is enabled in software standby mode DIVCR—Division Control Register H'5D System control...
Page 772 MSTCR—Module Standby Control Register H'5E System control PSTOP — MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0 Initial value Read/Write — Module standby 0 0 A/D converter operates normally (Initial value) 1 A/D converter is in standby state Module standby 1 0 Refresh controller operates normally (Initial value) 1 Refresh controller is in standby state Module standby 2...
Page 773 CSCR—Chip Select Control Register H'5F System control CS7E CS6E CS5E CS4E — — — — Initial value Read/Write — — — — Chip select 7 to 4 enable Bit n CSnE Description Output of chip select signal CSn is disabled (Initial value) Output of chip select signal CSn is enabled (n = 7 to 4)
Page 774 TSTR—Timer Start Register H'60 ITU (all channels) — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write — — — Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2 0 TCNT2 operates independently 1 TCNT2 is synchronized...
Page 775 TMDR—Timer Mode Register H'62 ITU (all channels) — FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value Read/Write — PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally...
Page 776 TFCR—Timer Function Control Register H'63 ITU (all channels) — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value Read/Write — — Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4 0 GRA4 operates normally...
Page 777 TCR0—Timer Control Register 0 H'64 ITU0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 TCNT Clock Source Internal clock: ø Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input...
Page 778 TIOR0—Timer I/O Control Register 0 H'65 ITU0 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 GRA Function GRA is an output No output at compare match compare register 0 output at GRA compare match...
Page 779 TIER0—Timer Interrupt Enable Register 0 H'66 ITU0 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA flag is disabled 1 IMIA interrupt requested by IMFA flag is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB flag is disabled 1 IMIB interrupt requested by IMFB flag is enabled...
Page 780 TSR0—Timer Status Register 0 H'67 ITU0 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] TCNT = GRA when GRA functions as an output compare register.
Page 781 TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0 Initial value Read/Write Up-counter GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0 Initial value Read/Write Output compare or input capture register TCR1—Timer Control Register 1 H'6E...
Page 782 TIOR1—Timer I/O Control Register 1 H'6F ITU1 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER1—Timer Interrupt Enable Register 1 H'70 ITU1 — — — — —...
Page 783 GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR2—Timer Control Register 2 H'78 ITU2...
Page 784 TIOR2—Timer I/O Control Register 2 H'79 ITU2 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER2—Timer Interrupt Enable Register 2 H'7A ITU2 — — — — —...
Page 785 TCNT2 H/L—Timer Counter 2 H/L H'7C, H'7D ITU2 Initial value Read/Write Phase counting mode: up/down counter Other modes: up-counter GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2 Initial value...
Page 786 TCR3—Timer Control Register 3 H'82 ITU3 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR3—Timer I/O Control Register 3 H'83 ITU3 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value...
Page 787 TSR3—Timer Status Register 3 H'85 ITU3 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Bit functions are the same as for ITU0 Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 1 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF...
Page 788 GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3 Initial value Read/Write Used to buffer GRA BRB3 H/L—Buffer Register B3 H/L H'8E, H'8F ITU3 Initial value...
Page 789 TOER—Timer Output Enable Register H'90 ITU (all channels) — — EXB4 EXA4 Initial value Read/Write — — Master enable TIOCA3 0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA4 0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR settings...
Page 790 TOCR—Timer Output Control Register H'91 ITU (all channels) — XTGD — — — — OLS4 OLS3 Initial value Read/Write — — — — — Output level select 3 0 TIOCB , TOCXA , and TOCXB outputs are inverted 1 TIOCB , TOCXA , and TOCXB outputs are not inverted Output level select 4 0 TIOCA , TIOCA , and TIOCB outputs are inverted 1 TIOCA , TIOCA , and TIOCB outputs are not inverted...
Page 791 TCR4—Timer Control Register 4 H'92 ITU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR4—Timer I/O Control Register 4 H'93 ITU4 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value...
Page 792 TCNT4 H/L—Timer Counter 4 H/L H'96, H'97 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4...
Page 793 BRB4 H/L—Buffer Register B4 H/L H'9E, H'9F ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. TPMR—TPC Output Mode Register H'A0 — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Group 0 non-overlap 0 Normal TPC output in group 0 Output values change at compare match A in the selected ITU channel...
Page 794 TPCR—TPC Output Control Register H'A1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 ITU Channel Selected as Output Trigger TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 0 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 1 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 2 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 3...
Page 795 NDERB—Next Data Enable Register B H'A2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 Description TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB ) TPC outputs TP to TP are enabled (NDR15 to NDR8 are transferred to PB to PB )
Page 796 NDRB—Next Data Register B H'A4/H'A6 • Same trigger for TPC output groups 2 and 3 Address H'FFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Store the next output data for Store the next output data for TPC output group 3 TPC output group 2 Address H'FFA6...
Page 797 NDRA—Next Data Register A H'A5/H'A7 • Same trigger for TPC output groups 0 and 1 Address H'FFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Store the next output data for Store the next output data for TPC output group 1 TPC output group 0 Address H'FFA7...
Page 798 TCSR—Timer Control/Status Register H'A8 — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Timer enable Clock select 2 to 0 0 Timer disabled ø/2 • TCNT is initialized to H'00 and halted ø/32 1 Timer enabled ø/64 • TCNT is counting ø/128 •...
Page 799 TCNT—Timer Counter H'A9 (read), H'A8 (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'AB (read), H'AA (write) WRST RSTOE — — — — — — Initial value Read/Write R/(W) — — — — — — Reset output enable 0 External output of reset signal is disabled 1 External output of reset signal is enabled Watchdog timer reset 0 [Clearing condition]...
Page 800 RFSHCR—Refresh Control Register H'AC Refresh controller SRFMD PSRAME DRAME CAS/ RFSHE — RCYCE Initial value Read/Write — Refresh cycle enable 0 Refresh cycles are disabled 1 Refresh cycles are enabled for area 3 Refresh pin enable RFSH Refresh signal output at the pin is disabled RFSH Refresh signal output at the...
Page 801 RTMCSR—Refresh Timer Control/Status Register H'AD Refresh controller CMIE CKS2 CKS1 CKS0 — — — Initial value Read/Write R/(W) — — — Clock select 2 to 0 Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Counter Clock Source Clock input is disabled ø/2 ø/8 ø/32...
Page 802 RTCNT—Refresh Timer Counter H'AE Refresh controller Initial value Read/Write Count value RTCOR—Refresh Time Constant Register H'AF Refresh controller Initial value Read/Write Interval at which RTCNT and compare match are set...
Page 803 SMR—Serial Mode Register H'B0 SCI0 C/A GM STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 Clock Source ø clock Multiprocessor mode ø/4 clock 0 Multiprocessor function disabled ø/16 clock 1 Multiprocessor format selected ø/64 clock Stop bit length 0 One stop bit...
Page 804 BRR—Bit Rate Register H'B1 SCI0 Initial value Read/Write Serial communication bit rate setting...
Page 805 SCR—Serial Control Register H'B2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Bit 1 Bit 0 CKE1 CKE0 Clock Selection and Output Asynchronous mode Internal clock, SCK pin available for generic I/O Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode Internal clock, SCK pin used for clock output Synchronous mode...
Page 806 TDR—Transmit Data Register H'B3 SCI0 Initial value Read/Write Serial transmit data...
Page 807 SSR—Serial Status Register H'B4 SCI0 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit Multiprocessor bit transfer Multiprocessor bit value in Multiprocessor bit value in receive data is 0 transmit data is 0 Multiprocessor bit value in Multiprocessor bit value in receive data is 1...
Page 808 RDR—Receive Data Register H'B5 SCI0 Initial value Read/Write Serial receive data SCMR—Smart Card Mode Register H'B6 SCI0 — — — — SDIR SINV — SMIF Initial value Read/Write — — — — — Smart card interface mode select 0 Smart card interface function is disabled (Initial value) 1 Smart card interface function is enabled Smart card data invert...
Page 809 SMR—Serial Mode Register H'B8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H'B9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H'BA SCI1 MPIE...
Page 810 TDR—Transmit Data Register H'BB SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SSR—Serial Status Register H'BC SCI1 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Notes: Bit functions are the same as for SCI0. Only 0 can be written, to clear the flag.
Page 811 P1DDR—Port 1 Data Direction Register H'C0 Port 1 P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR Initial value Modes 1 to 4 Read/Write — — — — — — — — Initial value Modes 5 to 7 Read/Write...
Page 812 P2DR—Port 2 Data Register H'C3 Port 2 Initial value Read/Write Data for port 2 pins P3DDR—Port 3 Data Direction Register H'C4 Port 3 P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value Read/Write Port 3 input/output select 0 Generic input pin...
Page 813 P3DR—Port 3 Data Register H'C6 Port 3 Initial value Read/Write Data for port 3 pins P4DR—Port 4 Data Register H'C7 Port 4 Initial value Read/Write Data for port 4 pins P5DDR—Port 5 Data Direction Register H'C8 Port 5 — — —...
Page 814 P6DDR—Port 6 Data Direction Register H'C9 Port 6 — P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR Initial value Read/Write — Port 6 input/output select 0 Generic input 1 Generic output P5DR—Port 5 Data Register H'CA Port 5 —...
Page 815 P8DDR—Port 8 Data Direction Register H'CD Port 8 — — — P8 DDR P8 DDR P8 DDR P8 DDR P8 DD Initial value Modes 1 to 4 Read/Write — — — Initial value Modes 5 to 7 Read/Write — — —...
Page 816 P9DDR—Port 9 Data Direction Register H'D0 Port 9 — — P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR Initial value Read/Write — — Port 9 input/output select 0 Generic input 1 Generic output PADDR—Port A Data Direction Register H'D1 Port A PA DDR...
Page 817 PADR—Port A Data Register H'D3 Port A Initial value Read/Write Data for port A pins PBDDR—Port B Data Direction Register H'D4 Port B PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B input/output select 0 Generic input...
Page 818 P2PCR—Port 2 Input Pull-Up MOS Control Register H'D8 Port 2 P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Initial value Read/Write Port 2 input pull-up MOS control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input).
Page 819 P5PCR—Port 5 Input Pull-Up MOS Control Register H'DB Port 5 — — — — P5 PCR P5 PCR P5 PCR P5 PCR Initial value Read/Write — — — — Port 5 input pull-up MOS control 3 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input).
Page 820 DACR—D/A Control Register H'DE DAOE1 DAOE0 — — — — — Initial value Read/Write — — — — — D/A enable Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 Description — D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1...
Page 821 ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 — — — — — — Initial value Read/Write ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result ADDRC H/L—A/D Data Register C H/L H'E4, H'E5 — — — —...
Page 822 ADCR—A/D Control Register H'E9 TRGE — — — — — — — Initial value Read/Write — — — — — — — Trigger enable 0 A/D conversion cannot be externally triggered ADTRG 1 A/D conversion starts at the fall of the external trigger signal (...
Page 823 ADCSR—A/D Control/Status Register H'E8 ADIE ADST SCAN Initial value Read/Write R/(W) Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Group Channel Selection Selection Description Single Mode Scan Mode Scan mode AN , AN 0 Single mode...
Page 824 ABWCR—Bus Width Control Register H'EC Bus controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW0 ABW1 Mode 1, 3, 5, 6 Initial value Mode 2, 4, 7 Read/Write Area 7 to 0 bus width control Bits 7 to 0 ABW7 to ABW0 Bus Width of Access Area Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas...
Page 825 WCR—Wait Control Register H'EE Bus controller — — — — WMS1 WMS0 Initial value Read/Write — — — — Wait mode select 1 and 0 Wait count 1 and 0 Bit 3 Bit 2 Bit 1 Bit 0 WMS1 WMS0 Wait Mode Number of Wait States Programmable wait mode...
Page 826 MDCR—Mode Control Register H'F1 System control — — — — — MDS2 MDS0 MDS1 Initial value — — — Read/Write — — — — — Mode select 2 to 0 Bit 2 Bit 1 Bit 0 Operating mode — Mode 1 Mode 2 Mode 3 Mode 4...
Page 827 SYSCR—System Control Register H'F2 System control SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit...
Page 828 BRCR—Bus Release Control Register H'F3 Bus controller A23E A22E A21E — — — — BRLE Modes Initial value 1, 2, Read/Write — — — — — — — 5, 7 Initial value Modes 3, 4, 6 Read/Write — — — —...
Page 829 ISR—IRQ Status Register H'F6 Interrupt controller — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * IRQ to IRQ flags Bits 5 to 0 IRQ5F to IRQ0F Setting and Clearing Conditions [Clearing conditions] Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
Page 830 IPRA—Interrupt Priority Register A H'F8 Interrupt controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 831: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Software standby Mode 7 Hardware standby External bus released Reset Mode 1 to 4 P1 DDR WP1D Reset Mode 7 P1 DR Mode 1 to 6 WP1D: Write to P1DDR WP1: Write to port 1 RP1:...
Page 832: Port 2 Block Diagram
C.2 Port 2 Block Diagram Reset P2 PCR Software standby Mode 7 RP2P WP2P Hardware standby Reset External bus Mode 1 to 4 released P2 DDR WP2D Reset Mode 7 P2 DR Mode 1 to 6 WP2P: Write to P2PCR RP2P: Read P2PCR WP2D:...
Page 833: Port 3 Block Diagram
C.3 Port 3 Block Diagram Reset Hardware standby External Mode 7 bus released P3 DDR Write to external address WP3D Reset Mode 7 P3 DR Mode 1 to 6 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 n = 0 to 7...
Page 834: Port 4 Block Diagram
C.4 Port 4 Block Diagram 8-bit bus 16-bit bus mode mode Mode Mode 7 1 to 6 Reset P4 PCR RP4P WP4P Reset Write to external P4 DDR address WP4D Reset P4 DR Read external address WP4P: Write to P4PCR RP4P: Read P4PCR WP4D:...
Page 835: Port 5 Block Diagram
C.5 Port 5 Block Diagram Reset P5 PCR Software standby Mode 7 RP5P WP5P Hardware standby External bus Mode 1 to 4 released Reset P5 DDR WP5D Reset Mode 7 P5 DR Mode 1 to 6 WP5P: Write to P5PCR RP5P: Read P5PCR WP5D:...
Page 836: Port 6 Block Diagrams
C.6 Port 6 Block Diagrams Reset P6 DDR Bus controller WAIT WP6D Mode 7 input Reset enable P6 DR Bus controller WAIT WP6D: Write to P6DDR input WP6: Write to port 6 RP6: Read port 6 Figure C-6 (a) Port 6 Block Diagram (Pin P6...
Page 837 Reset controller P6 DDR Mode 7 WP6D Bus release enable Reset P6 DR BREQ input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-6 (b) Port 6 Block Diagram (Pin P6...
Page 838 Reset P6 DDR WP6D Reset P6 DR Bus controller Mode 7 Bus release enable BACK output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-6 (c) Port 6 Block Diagram (Pin P6...
Page 839 Software standby Mode 7 Hardware standby External bus released Reset Mode 7 P6 DDR WP6D Reset Mode 7 P6 DR Mode 1 to 6 AS output RD output HWR output LWR output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 6 to 3...
Page 840: Port 7 Block Diagrams
C.7 Port 7 Block Diagrams A/D converter Input enable Analog input RP7: Read port 7 n = 0 to 5 Figure C-7 (a) Port 7 Block Diagram (Pins P7 to P7 A/D converter Input enable Analog input D/A converter Output enable Analog output RP7: Read port 7 n = 6 and 7...
Page 841: Port 8 Block Diagrams
C.8 Port 8 Block Diagrams Reset P8 DDR WP8D Reset Refresh P8 DR controller Mode 7 Output enable RFSH output Interrupt controller WP8D: Write to P8DDR WP8: Write to port 8 input RP8: Read port 8 Figure C-8 (a) Port 8 Block Diagram (Pin P8...
Page 842 Reset Bus controller P8 DDR Reset output Mode 7 P8 DR Mode 1 to 6 Interrupt controller input WP8D Write to P8DDR WP8: Write to port 8 RP8: Read port 8 n = 1 to 3 Figure C-8 (b) Port 8 Block Diagram (Pins P8 , P8 , P8...
Page 843 Reset Mode 1 to 4 Bus controller P8 DDR WP8D output Reset Mode 6/7 P8 DR Mode 1 to 5 WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C-8 (c) Port 8 Block Diagram (Pin P8...
Page 844: Port 9 Block Diagrams
C.9 Port 9 Block Diagrams Reset P9 DDR WP9D Reset P9 DR SCI0 Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-9 (a) Port 9 Block Diagram (Pin P9...
Page 845 Reset P9 DDR WP9D Reset P9 DR SCI1 Output enable Serial transmit data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-9 (b) Port 9 Block Diagram (Pin P9...
Page 846 Reset P9 DDR WP9D Input enable Reset P9 DR Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 2 and 3 Figure C-9 (c) Port 9 Block Diagram (Pins P9 , P9...
Page 847 Reset P9 DDR WP9D Clock input Reset enable P9 DR Clock output enable Clock output Clock input WP9D: Write to P9DDR Interrupt WP9: Write to port 9 controller RP9: Read port 9 n = 4 and 5 input Figure C-9 (d) Port 9 Block Diagram (Pins P9 , P9...
Page 848: Port A Block Diagrams
C.10 Port A Block Diagrams Reset PA DDR WPAD Reset output enable PA DR Next data Output trigger DMA controller Output enable Transfer end output Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0 and 1 Figure C-10 (a) Port A Block Diagram (Pins PA , PA...
Page 849 Reset PA DDR WPAD Reset output enable PA DR Next data Output trigger Output enable Compare match output Input capture Counter clock WPAD: Write to PADDR input WPA: Write to port A RPA: Read port A n = 2 and 3 Figure C-10 (b) Port A Block Diagram (Pins PA , PA...
Page 850 Software standby External bus released Hardware standby Bus controller Chip select enable Address output Reset enable output WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 4 to 6...
Page 851 Software standby External bus released Hardware standby Bus controller Address output Reset enable WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Figure C-10 (d) Port A Block Diagram (Pin PA...
Page 852: Port B Block Diagrams
C.11 Port B Block Diagrams Reset PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Output enable Compare match output Input capture WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 0 to 3 Figure C-11 (a) Port B Block Diagram (Pins PB to PB...
Page 853 Reset PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Output enable Compare match output WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 4 and 5 Figure C-11 (b) Port B Block Diagram (Pins PB , PB...
Page 854 Reset PB DDR WPBD Reset output enable PB DR Next data Output trigger Bus controller outpu Chip select enable DMAC WPBD: Write to PBDDR DREQ0 WPB: Write to port B input RPB: Read port B Figure C-11 (c) Port B Block Diagram (Pin PB...
Page 855 Reset PB DDR WPBD Reset output enable PB DR Next data Output trigger DMAC WPBD: Write to PBDDR DREQ1 WPB: Write to port B input RPB: Read port B A/D converter ADTRG input Figure C-11 (d) Port B Block Diagram (Pin PB...
Page 856: Appendix D Pin States
Appendix D Pin States D.1 Port States in Each Mode Table D-1 Port States Hardware Software Bus- Program Standby Standby Released Execution, Name Mode Reset Mode Mode Mode Sleep Mode ø — Clock output T Clock output Clock output RESO RESO —...
Page 857 Table D-1 Port States (cont) Hardware Software Bus- Program Standby Standby Released Execution, Name Mode Reset Mode Mode Mode Sleep Mode to P5 1 to 4 to A 5, 6 keep Input port (DDR = 0) to A (DDR = 1) keep —...
Page 858 Table D-1 Port States (cont) Hardware Software Bus- Program Standby Standby Released Execution, Name Mode Reset Mode Mode Mode Sleep Mode to P8 1 to 6 keep Input port (DDR = 0) (DDR = 0) (DDR = 0) or to CS (DDR = 1) (DDR = 1) (DDR = 1)
Page 859: Pin States At Reset
D.2 Pin States at Reset RES goes low during the Reset in T1 State: Figure D-1 is a timing diagram for the case in which T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
Page 860 Reset in T2 State: Figure D-2 is a timing diagram for the case in which RES goes low during the T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state.
Page 861 Reset in T3 State: Figure D-3 is a timing diagram for the case in which RES goes low during the T3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state.
Page 862: Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
Page 863: Appendix F Product Code Lineup
Appendix F Product Code Lineup Table F-1 H8/3048 Series Product Code Lineup Package (Hitachi Product Type Product Code Mark Code Package Code) H8/3048 PROM HD6473048TF HD6473048TF 100-pin TQFP version version (TFP-100B) (ZTAT) HD6473048F HD6473048F 100-pin QFP (FP-100B) HD6473048VTF HD6473048VTF 100-pin TQFP...
Page 864 Table F-1 H8/3048 Series Product Code Lineup (cont) Package (Hitachi Product Type Product Code Mark Code Package Code) H8/3045 Mask HD6433045TF HD6433045(***)TF 100-pin TQFP version (TFP-100B) version HD6433045F HD6433045(***)F 100-pin QFP (FP-100B) HD6433045VTF HD6433045(***)VTF 100-pin TQFP version (TFP-100B) HD6433045VF HD6433045(***)VF...
Page 865: Appendix G Package Dimensions
Appendix G Package Dimensions Figure G-1 shows the FP-100B package dimensions of the H8/3048 Series. Figure G-2 shows the TFP-100B package dimensions. Unit: mm 16.0 ± 0.3 0.22 ± 0.05 0.08 M 0.20 ± 0.04 0° – 8° 0.5 ± 0.2 0.10 Dimension including the plating thickness Base material dimension...
Page 866 Unit: mm 16.0 ± 0.2 0.22 ± 0.05 0.08 0.20 ± 0.04 0° – 8° 0.5 ± 0.1 0.10 Dimension including the plating thickness Base material dimension Figure G-2 Package Dimensions (TFP-100B)
Page 867 Hardware Manual Publication Date: 1st Edition, January 1995 3nd Edition, October 1997 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Documentation Center Hitachi Microcomputer System Ltd. Copyright © Hitachi, Ltd., 1995. All rights reserved. Printed in Japan.

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