I 2 C Bus Status Register 0 To 2 (Ibsr0 To Ibsr2) - Fujitsu F2MC-16LX Hardware Manual

2
22.2.1 I C Bus Status Register 0 to 2 (IBSR0 to IBSR2)
The configuration and functions of I
described.
2
I C Bus Status Register 0 to 2 (IBSR0 to IBSR2)
Figure 22.2-2 shows the bit configuration of I
Figure 22.2-2 Bit Configuration of I
ch0:000070
ch1:000076
ch2:00007C
The function of each bit of the I
[bit 7] BB: Bus Busy
It is a bit shown the state of the I
0
1
[bit 6] RSC: Repeated Start Condition
It is a start condition detection repeatedly bit.
0
1
Is cleared either by writing "0" in INT bit, with no addressing on the slave connection, or by detecting the
start condition during the halted bus, or by detecting the stop condition.
[bit 5] AL: Arbitration Lost
It is an arbitration lost detection bit.
0
1
It is cleared by writing "0" in INT bit.
2
C bus status register 0 to 2 (IBSR0 to IBSR2) are
2
C Bus Status Register 0 to 2(IBSR0 to IBSR2)
7 6 5 4
H
BB RSC AL LRB TRX AAS GCA FBT
H
H
R R R R
2
C bus status registers 0 to 2 (IBSR0 to IBSR2) is described as follows:
2
C bus.
Stop condition is detected.
Start condition is detected. (The bus is used.)
The start condition is not repeatedly detected.
The start condition was detected in the bus Occupied again.
The arbitration lost is not detected.
When arbitration lost has occurred on master transmission, or when other
systems are using the bus, "1" was written in MSS bit.
2
C bus status registers 0 to 2 (IBSR0 to IBSR2).
IBSR0 to IBSR2
3 2 1 0
2
I C Bus status register
Initial value
R R R R
2
CHAPTER 22 I C INTERFACE
00000000
B
525