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12.4.1
Timer Control Status Register, Upper Byte (TMCSRH0/
TMCSRH1)
High-order bit11 to bit8 and low-order bit7 of the timer control status registers
(TMCSR0/TMCSR1) are used to select the operating mode of the 16-bit reload timer and
set the operating conditions. This section describes low-order bit7: the MOD0 bit.
■ Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1)
Figure 12.4-2 Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1)
Address
bit
TMCSRH0
000083
H
TMCSRH1
000087
H
R/W
Read/Write
Not used
X
Undefined
Initial value
Machine cycle. Value in parentheres ( ) indicates the value when machine clock is 16MHz
15
14
13
12
11
CSL1
R/W
10
9
8
7
CSL0
MOD1
MOD2
MOD0
R/W R/W R/W
R/W
Operating mode selection bit
MOD2 MOD1 MOD0
Input pin function
0
0
0
Trigger disabled
0
0
1
0
1
0
Trigger input
0
1
1
1
X
0
Gate input
1
X
1
MOD2 MOD1 MOD0
Input pin function
X
0
0
X
0
1
X
1
0
Trigger input
X
1
1
Count clock selection bit
CSL1 CSL0
Function
0
0
0
1
Internal clock mode
1
0
1
1
Event count mode
CHAPTER 12 16-BIT RELOAD TIMER
6
0
Initial value
(TMCSR:L)
----00000
(Internal clock mode)
Valid edge and level
Rising edge
Falling edge
Both edges
"L" level
"H" level
Operating mode selection bit
(Event count mode)
Valid edge
Rising edge
Falling edge
Both edges
Count clock
1
(0.125 s)
2
3
2
(0.5 s)
5
2
(2.0 s)
External event input
B
237
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