Control Status Register (Tmcsr) - Fujitsu FR60 Hardware Manual

CHAPTER 6 16-BIT RELOAD TIMER
6.2.1

Control Status Register (TMCSR)

The control status register (TMCSR) controls the operating modes and interrupts of
the 16-bit timer.
■ Bit Configuration of the Control Status Register (TMCSR)
Figure 6.2-2 Bit Configuration of the Control Status Register (TMCSR)
bit
Address: 00004E
Reserved Reserved Reserved Reserved
H
000056
H
00005E
H
bit
MOD0
R/W
Rewrite bits other than the UF, CNTE, and TRG bits only when CNTE=0.
The control status register (TMCSR) supports simultaneous writing.
When write to bit5, bit12, and bit13, be sure to write "0".
■ Bit Functions of the Control Status Register (TMCSR)
The following describes the bit functions of the control status register (TMCSR).
[bit15] (Reserved)
This bit is unused.
[bit14] (Reserved)
This bit is unused.
[bit13] (Reserved)
Be sure to write "0" at write.
[bit12] (Reserved)
Be sure to write "0" at write.
[bit11, bit10] CSL1, CSL0 (Count source SeLect)
These bits are the count source select bits. Count sources can be selected from the internal
clock or the external event. Table 6.2-1 shows the count sources that can be selected using
these bits. Countable edges used when external event count mode are set using the MOD1
and MOD0 bits
272
15 14 13
- - (R/W)
7 6 5
Reserved Reserved
R R/W
12 11 10
CSL1 CSL0
(R/W) R/W R/W
4 3 2
RELD INTE UF
R/W R/W R/W
9 8 Initial value
--XX0000
MOD2 MOD1
00000000
R/W R/W
1 0
CNTE TRG
R/W R/W
B
B