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CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK
10.2.3 External Interrupt Level Setting Register (ELVR: External
Level Register)
The external level register (ELVR) selects the level at which an interrupt request is
detected.
I External level register (ELVR: External Level Register)
The register configuration of the external level register is shown below.
ELVR 0
Address:0000CC
H
ELVR 1
Address:0000CE
H
INT0-15 has two bits that specify the operations shown below. If you specify that the request be
detected at a low or high level, even when each bit of the EIRR is cleared, the corresponding
bits are set again when active-level input occurs.
Table 10.2-1 "ELVR allocation table" is the ELVR allocation table.
Table 10.2-1 ELVR allocation table
LBx
0
0
1
1
252
7
6
5
LB3
LA3
LB2
LA2
15
14
1 3
12
LB 7
LA 7
LB 6
LA 6
7
6
5
4
LB 11 LA 11 LB 10 LA 10
15
14
1 3
12
LB 1 5 LA 1 5 LB 14 LA 14 LB 13 LA 13 LB 12 LA 12
LAx
0
Low level request
1
High level request
0
Rising edge request
1
Falling edge request
4
3
2
1
LB1
LA1
LB0
11
1 0
9
LB 5
LA 5
LB4
3
2
1
LB 9
L A 9
LB8
1 1
1 0
9
Operation
0
Initial value
LA0
00000000
[ R/W]
8
Initial value
LA 4
00 000000
[ R/ W]
0
Initial value
LA8
0 0000000
[ R/ W]
8
Initial value
000 00000
[ R/W ]
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