Interrupt Level Mask Register (Ps: Ilm) - Fujitsu MB90460 Series Hardware Manual

3.7.6

Interrupt Level Mask Register (PS: ILM)

The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the
interrupt currently accepted by the CPU.CHAPTER 7 INTERRUPT
■ Interrupt Level Mask Register (ILM)
Figure 3.7-12 shows the configuration of the interrupt level mask register (ILM). See "CHAPTER 7
INTERRUPT", for details about interrupts.
Figure 3.7-12 Configuration of the Interrupt Level Mask Register (ILM)
The interrupt level mask register (ILM) indicates the level of the interrupt currently accepted by the CPU.
The level is compared with the value of the IL0 to IL2 bits of the interrupt control register (ICR00 to
ICR15) set according to the interrupt request from the peripheral function. If the interrupt enable flag has
been set to enable (CCR: I = 1), the CPU processes the instruction only when the value (interrupt level) of
the interrupt request is smaller than the value indicated by these bits.
• When an interrupt is accepted, the interrupt level value is set in the interrupt level mask register (ILM).
Thereafter, interrupts with the same or lower level are not accepted.
• The interrupt level is set to the highest level, which is the interrupts disabled status, because the interrupt
level mask register (ILM) is initialized to all 0's by a reset.
• Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to
the interrupt level mask register (ILM), only the lower 3 bits of the data are used.
• Interrupt level mask register (ILM) and interrupt level priority
Table 3.7-3 Interrupt Level Mask Register (ILM) and Interrupt Level Priority
ILM2
0
0
0
0
1
1
1
1
bit 15
ILM2
Default value ⇒
0
ILM1 ILM0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
14 13
ILM1 ILM0 : ILM
0 0
Interrupt level
0 Highest (interrupts disabled)
1
2
3
4
5
6
7
CHAPTER 3 CPU
Interrupt level priority
Lowest
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