23.2.4 Chip Selector Active Level Register (CALR)
This section describes the configuration and functions of the chip selector active level
register (CALR).
I Chip selector active level register (CALR)
The diagram below shows the bit configuration of the chip selector active level register (CALR).
15
0000C9
-
H
(-)
(-)
[Bit 15-12] Unused bits
These bits are unused. In read operations, the return value for these bits is undefined.
[Bit 11-8] ACTL3-0
These bits are used to set the active level of each CS3-0 pin.
The operational settings are as follows.
•
"0": Each CS3-0 pin outputs "L" after decoding.
•
"1": Each CS3-0 pin outputs "H" after decoding.
Note:
•
Before changing the active level, prohibit output via the chip selection control register.
•
Writing these bits in units of words is prohibited. Always write these bits in units of bytes.
This will prevent the enabling of output at the same time that the active level is changed.
14
13
12
11
-
-
-
ACTL3 ACTL2 ACTL1 ACTL0
(-)
(-)
(-)
(R/W) (R/W) (R/W) (R/W)
(-)
(-)
(-)
(0)
CHAPTER 23 CHIP SELECTION FACILITY
10
9
8
CALR
Chip selector active level register
Read/write
(0)
(0)
(0)
Initial value
445