External Interrupt Request Level Setting Register (Elvr) - Fujitsu FR60 Hardware Manual

CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
9.2.3

External Interrupt Request Level Setting Register (ELVR)

This section describes the bit configuration and functions of the external interrupt
request level setting register (ELVR).
■ External Interrupt Request Level Setting Register (ELVR: External Level Register)
Figure 9.2-4 shows the bit configuration of the external interrupt request level setting register
(ELVR).
Figure 9.2-4 Bit Configuration of the External Interrupt Request Level Setting Register (ELVR)
Address: 000042
Address: 000043
The external interrupt request level setting register (ELVR) selects how a request is detected.
Two bits are assigned to each of INT0 to INT7, which results in the settings shown in Table 9.2-
1. Even though the bits of the EIRR are cleared while the request input is a level, the pertinent
bits are set again as long as the input is an active level.
Table 9.2-1 Settings of the LBn and LAn Bits
LBn
0
0
1
1
Note:
A falling edge is always detected at NMI (except in the stop state).
In the stop state, the "L" level is detected.
INT should be set "H" level at stop.
320
bit 15 14 13
LB7 LA7 LB6
H
R/W R/W R/W
bit 7 6 5
LB3 LA3 LB2
H
R/W R/W R/W
LAn
0 "L" level indicates the existence of a request.
1 "H" level indicates the existence of a request.
0 A rising edge indicates the existence of a request.
1 A falling edge indicates the existence of a request.
12 11 10 9
LA6 LB5 LA5 LB4
R/W R/W R/W R/W
4 3 2 1
LA2 LB1 LA1 LB0
R/W R/W R/W R/W
Operation
8 Initial value
00000000
LA4
B
R/W
0 Initial value
00000000
LA0
B
R/W