Register Of Dtp/External Interrupt - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
16.2

Register of DTP/External Interrupt

This section describes the configuration and functions of registers used for the DTP
and external interrupts.
■ Register List of DTP/External Interrupt
Figure 16.2-1 shows the register list of the DTP/external interrupts.
bit
Address : 00003C
H
bit
Address : 00003D
H
bit
Address : 00003E
H
bit
Address : 00003F
H
■ DTP/Interruption Permission Register (ENIR: Enable Interrupt Request Register)
Figure 16.2-2 shows the bit configuration of the DTP and enable interrupt register (ENIR).
Figure 16.2-2 Bit Configuration of the DTP and the Enable Interrupt Request Register (ENIR)
ENIR
Address : 00003C
The DTP and the enable interrupt register (ENIR) determine to issue the request to the interrupt controller
by using the device pin as the external interrupt and the DTP request input. The pin corresponding to the
bits set to "1" in the ENIR register is used to input an external interrupt or DTP request to issue the requests
to the interrupt controller. The pin corresponding to the bits set to "0" holds the external interrupt or DTP
request input factor but issues no request to the interrupt controller.
CM44-10137-6E
Figure 16.2-1 Register List of DTP/external Interrupt
7 6 5 4
EN7 EN6 EN5 EN4
15 14 13 12
ER7 ER6 ER5 ER4
7 6 5 4
LB3 LA3 LB2 LA2
15 14 13 12
LB7 LA7 LB6 LA6
7 6
bit
EN7 EN6 EN5
H
R/W R/W R/W
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 16 DTP/EXTERNAL INTERRUPT
3 2 1
EN3 EN2 EN1
11 10 9
ER3 ER2 ER1
3 2 1
LB1 LA1 LB0
11 10 9
LB5 LA5 LB4
5 4 3 2
EN4 EN3 EN2
R/W R/W R/W
16.2 Register of DTP/External Interrupt
0
DTP/Interrupt Enable Register
EN0
(ENIR)
8
DTP/Interrupt Factor Register
ER0
(EIRR)
0
Request level setting register
LA0
(ELVR)
8
Request level setting register
LA4
(ELVR)
1 0
Initial value
EN1 EN0
00000000
R/W R/W
B
359