Register; External Interrupt Enable Register (Enir); External Interrupt Request Register (Eirr); Request Level Setting Register (Elvr) - Fujitsu ALL Series Application Note

2.3 Register

2.3.1 External Interrupt Enable Register (ENIR)

This 16 bit register contains the interrupt enable bits for each external interrupt channel.
Writing '1' to these bits enables the corresponding external interrupt requests.

2.3.2 External Interrupt Request Register (EIRR)

This 16 bit register contains the flag which is set if the specified interrupt event occurs at the
corresponding external interrupt pin. Writing "0" to it clears the request. The interrupt request
bit must be cleared by the ISR. These flags can also be used for polling if the corresponding
Interrupt Enable bit is disabled.

2.3.3 Request Level Setting Register (ELVR)

This register contains a pair of control bits LBx:LAx for each channel for the detection kind.
The following table shows the possible settings:
Where x = 0 to 7 for ELVR0

2.3.4 Port Input Enable Register

External Interrupts need a port pin that is set to digital input mode. Please enable the
corresponding input pin before enabling the external interrupt. See pin assignment in
datasheet to determine which port pin must be enabled.
Example:
External Interrupt 0 shall be used. This is shown as INT0 in pin assignment. On MB96340
series, this function shares pin P07_0. Hence, this pin must be enabled for input:
PIER07_IE0 = 1;
© Fujitsu Microelectronics Europe GmbH
EXTERNAL INTERRUPTS
Chapter 2 External Interrupts
LBx LAx Functionality
0 0 "L" Level Input
0 1 "H" Level Input
1 0 Rising Edge Pin Input
1 1 Falling Edge Pin Input
Table 2-1: ELVR
and 8 to 15 for ELVR1
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