Clock Select Register (Ckscr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 5 CLOCK
5.3

Clock Select Register (CKSCR)

The clock select register (CKSCR) switches the clock mode between the main, sub, and
PLL clocks, and selects the oscillation stabilization wait time and the PLL clock
frequency multiplier.
Configuration of Clock Select Register (CKSCR)
Figure 5.3-1 shows the clock selection register (CKSCR) configuration. Table 5.3-1 summarizes the
functions of the clock selection register bits.
bit15 bit14 bit13 bit12 bit11 bit10 bit 9
Address
0000A1
H
R/W : Readable/Writable
: Read only
R
Initial value
132
Figure 5.3-1 Configuration of Clock Select Register (CKSCR)
SCM MCM WS1 WS0 SCS
R R R/W R/W R/W R/W R/W R/W
bit 8 bit 7
MCS CS1 CS0 (LPMCR)
Multiplication factor selection bit
CS1 CS0
Each value in parentheses ( ) represents the period
at 64 MHz.
0 0 1×HCLK ( 6MHz)
0 1 2×HCLK (12MHz)
4×HCLK (24MHz)
1 0
1 1 Disable to setting
Machin clock selection bit
MCS
0
PLL clock selection
1
Main clock selection
Sub clock selection bit
SCS
0
Sub clock selection
1
Main clock selection
Oscillation stabilization wait time selection bit
WS1 WS0
Each value in parentheses ( ) represents the period
at 64 MHz.
/HCLK ( Approx. 170.7 µs )
0 0
10
2
0 1 13
2 /HCLK ( Approx. 1.36 ms )
15
1 0 2 /HCLK ( Approx. 5.46 ms )
1 1 2 17 /HCLK ( Approx. 21.84 ms )*
*:2 16 /HCLK (approx. 10.92 ms) at pwer-on reset
Machine clock display bit
MCM
0 During operating at PLL clock
1 During operating at Main clock
Sub clock display bit
SCM
0
Sub clock selection
1
Main clock selection
bit 0
Initial value
11111100
B