Analogue Input Enable Register; Low Noise Output Select Register - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

8.3.5 Analogue Input Enable Register

Port 5 analogue enable register
Address : 00001C
Read/write
Initial value
This register controls the .behaviour of port 5.
0
1
Note: When an intermediate voltage level is applied to the pin during port input mode, a
leakage current will be induced. In this case, configure the pin to analogue input mode
instead.

8.3.6 Low Noise Output Select Register

Low Noise Output Select register (Upper)
Address : 0000A3
Read/write
Initial value
Low Noise Output Select register (Lower)
Address : 0000A2
Read/write
Initial value
These two register are used to select the low noise output buffer for Port 0 to Port A and the TX output of
IE bus.
[bit 15 - 12] - unused bits
[bit 11] - LNB controls TX pin of IE bus
0
1
[bit 10] - LNA controls Port A
0
1
MB90580 Series
7 6 5
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
H
R/W R/W R/W
1 1 1
Port input mode
Analogue input mode
15 14 13
H
7 6 5
LN7 LN6 LN5
H
R/W R/W R/W
0 0 0
Normal output buffer
Low noise output buffer
Normal output buffer
Low noise output buffer
8.3 Registers and register details
4 3 2 1
R/W R/W R/W R/W
1 1 1 1
12 11 10
LNB LNA LN9
R/W R/W R/W
0 0
4 3 2
LN1
LN4 LN3 LN2
R/W R/W R/W R/W
0 0 0
Bit number
0
ADER
R/W
1
[initial value]
9 8
Bit number
LN8 LNSRH
R/W
0 0
1 0 Bit number
LN0
LNSRL
R/W
0 0
[initial value]
[initial value]
Chapter 8: Parallel Ports 107