Area Select Registers (Asr) And Area Mask Registers (Amr) - Fujitsu MB91150 Series Hardware Manual

CHAPTER 4 BUS INTERFACE
4.3.1 Area Select Registers (ASR) and Area Mask Registers
(AMR)
The area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5)
specify the ranges at which chip select areas 1 to 5 are allocated in address space.
I Area select registers (ASR) and Area mask registers (AMR)
The configurations of the ASRs and AMRs are as follows.
❍ ASR1 to ASR5
15
AMR1 A31
AMR2 A31
AMR3 A31
AMR4 A31
AMR5 A31
❍ AMR1 to AMR5
15
ASR1 A31
ASR2 A31
ASR3 A31
ASR4 A31
ASR5 A31
ASR1 to ASR5 and AMR1 to AMR5 specify the ranges at which chip select areas 1 to 5 are
allocated in address space.
ASR1 to ASR5 specify the higher 16 bits (A31 to A16) of an address and AMR1 to AMR5 mask
the corresponding address bits. Each bit of AMR1 to AMR5 indicates "care" if it is set to 0. The
bit indicates "don't care" if it is set to 1.
"care" indicates that a value of 0 or 1 in the corresponding ASR bit is treated as such in the
selection of the address space. On the other hand, "don't care" indicates that the address space
for both 0 and 1 is selected regardless of the actual value of the corresponding ASR bit.
Some examples of chip select area specification with the ASR and AMR are shown below.
Example 1
ASR1 = 00000000 00000011
AMR1 = 00000000 00000000
In this example, a 64-KB area in address space is allocated to area 1 as follows because the
ASR1 bits are set to 1 and the corresponding AMR1 bits are set to 0:
102
14 13 12
A30 A29
A30 A29
A30 A29
A30 A29
A30 A29
14 13 12
A30 A29
A30 A29
A30 A29
A30 A29
A30 A29
B
B
Initial value
2 1 0
A18 A17 A16 0001
A18 A17 A16 0002
A18 A17 A16 0003
A18 A17 A16 0004
A18 A17 A16 0005
Initial value
2 1 0
A18 A17 A16 0000
A18 A17 A16 0000
A18 A17 A16 0000
A18 A17 A16 0000
A18 A17 A16 0000
Access
W
W
W
W
W
Access
W
W
W
W
W