Chip Select Area Mask Register (Cmrx) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 23 CHIP SELECTION FACILITY

23.2.1 Chip Select Area MASK Register (CMRx)

This section describes the configuration and functions of the chip selection area
MASK register (CMRx).
I Chip selection area MASK register (CMRx)
The diagram below shows the bit configuration of the chip selection area MASK register
(CMRx).
0000C0 7
H
0000C2 M7
H
0000C4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
H
0000C6 (0)
H
[bit7-0]M7-M0
[Bit 7-0] M7-M0
These bits are used to specify an address decode area for the chip selection pin. Set the
corresponding bit to "1" for masking.
These bits are used to specify an area of 128 KB or more.
Note:
If all bits are masked, no external access is activated.
442
6 5 4 3
M6 M5 M4 M3
(0) (0) (0) (1)
2 1 0 CMRx
M2 M1 M0 Chip selection area MASK register
Read/write
(1) (1) (1) Initial value