Clock Control Block - Fujitsu F2MC-8L Family series Hardware Manual

CPU
Clock
oscillator
From time-base timer
Power-on reset
Watchdog timer reset
External reset
Software reset
HARDWARE CONFIGURATION

2.1.4 Clock Control Block

This block controls the standby operation and software reset.
(1) Machine clock control block diagram
(a) Machine clock control section
HC1
Stop release signal
Selector
HC3
Option
(b) Reset control section
Reset control
(2) Register list
Address: 0008
H
STP SLP
Clock control
8 bits
STBC Standby control register
2– 9
SPL
Pin state
Stop
CPU operation clock
Peripheral operation clock
Internal reset signal