Block Diagram Of The Clock Generation Block - Fujitsu MB90460 Series Hardware Manual

CHAPTER 5 CLOCK
5.2

Block Diagram of the Clock Generation Block

The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait interval selector
■ Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block.
Figure 5.2-1 also includes the standby control circuit and time-base timer circuit.
Low power mode control register (LPMCR)
Pin
RSTX
Release reset
Cancel interrupt
Clock generator
Pin
X0
X1 Pin
80
Figure 5.2-1 Block Diagram of the Clock Generation Block
STP SLP SPL TMD
RST
3
Clock selector
x1 x2 x3 x4
PLL multipiler
RESV MCM
circuit
Clock selection register (CKSCR)
Divide-
by-2
Main clock
System clock
generation circuit
CG1 CG0 RESV
Pin high
impedance
control circuit
Internal reset
generation
circuit
CPU intermittent
operation selecter
CPU clock
control circuit
RST
Standby control
circuit
Machine clock
Peripheral clock
control circuit
Oscillation stabiliz-
-ation wait is passed
2
2
WS1 WS0 RESV MCS CS1
Divide-
Divide-
by-512
by-2
Pin Hi-z control
Internal reset
Select intermittent cycles
CPU clock
Stop and sleep signals
Stop signal
Peripheral clock
Oscillation stabilization
wait interval selector
CS0
Divide-
Divide- Divide-
by-4
by-4 by-4
Time-base timer