System Clock Control Register (Sycc); Figure 3.6-5 System Clock Control Register (Sycc) - Fujitsu F2MC-8L Series Hardware Manual

3.6.3

System Clock Control Register (SYCC)

The system clock control register (SYCC) is used to switch between the main clock
and subclock, select the main clock speed, and select the oscillation stabilization
delay time.
Structure of System Clock Control Register (SYCC)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address
0007
H SCM
R
R/W : Readable/writable
R : Read-only
: Unused
X : Indeterminate
M : Option-dependent
: Initial value

Figure 3.6-5 System Clock Control Register (SYCC)

WT1 WT0 SCS CS1 CS0
R/W R/W R/W R/W R/W
Initial value
X--MM100
B
Main clock speed select bit
CS1 CS0
Instruction cycle (at F
0 0 64/F (15.2 s)
CH
0 1 16/F (3.81 s)
CH
1 0 8/F (1.90 s)
CH
1 1 4/F (0.95 s)
CH
SCS System clock select bit
Select subclock (32 kHz) mode.
0
Select main clock mode.
1
Oscillation stabilization delay time select bit
WT1 WT0
main clock oscillation stabilization delay time
depending on timebase timer output (at F
4
0 0
Approx. 2 /F (approx. 0 ms)
CH
12
0 1 Approx. 2 /F
CH
16
1 0 Approx. 2 /F
CH
18
1 1 Approx. 2 /F
CH
SCM System clock monitor bit
Subclock (with the main clock off or in oscillation
0
stabilization delay state)
1 Main clock
FCH: Main clock source oscillation
= 4.2 MHz)
CH
= 4.2 MHz)
CH
(approx. 1.0 ms)
(approx. 15.6 ms)
(approx. 62.4 ms)
3.6 Clocks
65