Clock Control Register (Iccr) - Fujitsu F2MC-16LX Hardware Manual

2
CHAPTER 22 I C INTERFACE

22.2.3 Clock Control Register (ICCR)

This section describes the configuration and functions of the clock control register
(ICCR).
I Clock control register (ICCR)
The diagram below shows the bit configuration of the clock control register (ICCR).
Clock control register
Address: 00008A
The functions of the clock control register (ICCR) are as follows.
[Bits 7, 6] Unused
These bits are unused.
[Bit 5] EN: ENable
This bit is used to enable I
0
1
• When this bit is set to "0", each bit of the BSR register and the BCR register (except for the
BER and BEIE bits) is cleared.
• Setting the BER bit clears this bit.
[Bits 4 to 0] CS4-0: Clock Period Select 4-0
These bits are used to set the frequency of the serial clock. The shift clock frequency fsck is
set in this register according to the following formula.
Note:
The "+ 4" term in the formula reflects the minimum overhead for checking whether the output
level of the SCL pin has changed. If the rising edge of the SCL pin is delayed or a slave
device delays the clock, the overhead increases. Do not set the serial clock frequency to 100
kHz or more.
The values for m and n must be as shown in Table 22.2-1 "Serial clock frequency settings"
for CS4-0.
432
7 6
H
- -
Read/write
(-) (-) (R/W) (R/W)(R/W)(R/W)(R/W)(R/W)
Initial value
(-) (-)
2
C interface operation.
Operation disabled
Operation enabled
φ
fsck =
m × n + 4
5 4 3 2 1
EN CS4 CS3 CS2 CS1 CS0
(0) (X) (X) (X) (X)
φ: Machine clock
0 Bit number
ICCR
(X)