Clock Generation Control - Fujitsu MB91260B Series Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.11

Clock Generation Control

The generation and control of each type of clock signal are described below.
The internal operation clock signals for the MB91260B series are generated as follows:
• Base clock signal:
• Internal clock signals: Operation clock signals to be supplied to different parts are
For information on the registers and flags mentioned below, see "3.11.5 Block Diagram
of the Clock Generation Control Unit" and "3.11.6 Registers in the Clock Generation
Control Unit".
■ Selecting the Source Clock Signal
The source clock signal is selected as follows.
The oscillating signal generated by the internal oscillator circuit with an oscillator connected to the external
oscillation pins X0 and X1 is used as the source clock signal.
The MB91260B series itself is the source of all clock signals available, including the external bus clock
signal.
The main clock signal can be selected arbitrarily during operation between the external oscillation pins and
internal oscillator circuit.
• Main clock signal: Generated from the X0/X1 pin input to be used as a high-speed clock signal.
The internal base clock signal to be generated is selected from among the following source clock signals:
• Generated by frequency-halving the main clock signal
• Generated by multiplying the main clock signal using a PLL
φ is the base clock that is generated from the source clock divided by two or by using the PLL oscillation.
Therefore, the system base clock is a clock generated in the above-mentioned internal base clock
generation.
The source clock signal is selected by setting the CLKR (clock source control register).
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A base clock signal is generated by frequency-halving the
source clock signal or PLL oscillation.
generated by frequency-dividing the base clock.