Reset And Power Supply Supervisor; Power-On Reset (Por)/Power-Down Reset (Pdr); Programmable Voltage Detector (Pvd); Figure 5. Power On Reset/Power Down Reset Waveform - ST STM32H7 3 Series Application Note

AN4938
1.3

Reset and power supply supervisor

1.3.1

Power-on reset (POR)/power-down reset (PDR)

The devices have an integrated POR/PDR circuitry that allows a proper operation starting
from 1.71 V.
The devices remain in reset mode when V
without the need for an external reset circuit. For more details concerning the power
on/power-down reset threshold, refer to the electrical characteristics of the datasheet.
1. t
RSTTEMPO
is 1.62 V (typical). Refer to the device datasheets for the actual values.
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
1.3.2

Programmable voltage detector (PVD)

The PVD can be used to monitor the V
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to
indicate if V
to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers.
The PVD output interrupt can be generated when V
and/or when V
edge configuration. As an example the service routine could perform emergency shutdown
tasks.

Figure 5. Power on reset/power down reset waveform

is approximately 2.6 ms. VPOR/PDR rising edge is 1.66 V (typical) and VPOR/PDR falling edge
is higher or lower than the PVD threshold. This event is internally connected
DD
rises above the PVD threshold depending on EXTI line16 rising/falling
DD
DocID029918 Rev 1
is below a specified threshold, VPOR/PDR,
DD
power supply by comparing it to a threshold
DD
drops below the PVD threshold
DD
Power supplies
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