Reset & Power Supply Supervisor; Power-On Reset (Por)/Power-Down Reset (Pdr); Programmable Voltage Detector (Pvd); Figure 4. Power On Reset/Power Down Reset Waveform - ST STM32F74 Series Getting Started

AN4661
μF) must be connected.
2. V
REF+
3. V is either connected to V
REF-
4. 19 is the number of V
5. Refer to
BYPASS_REG and PDR_ON pins.
1.3 Reset & power supply supervisor
1.3.1

Power-on reset (POR)/power-down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from
1.8 V.
The device remains in reset mode when V
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power-down reset threshold, refer to the electrical characteristics of the
datasheet.
1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge
is 1.70 V (typ.). Refer to STM32F756xx datasheets for the actual value.
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
1.3.2

Programmable voltage detector (PVD)

The PVD can be used to monitor the V
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
is either connected to V
REF+
REF-
and V
DD SS
Section 1.3.7: Regulator ON/OFF and internal reset ON/OFF availability

Figure 4. Power on reset/power down reset waveform

or to V (depending on package).
DDA
or to V (depending on package).
SSA
inputs.
/V is below a specified threshold,
DD DDA
power supply by comparing it to a threshold
DD
DocID027559 Rev 2
Power supplies
to connect
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